able (OE), and three-state drivers. Writing to the device is ac-
complished by taking Chip Enable One (CE
1
) and Write En-
able (WE) inputs LOW and Chip Enable Two (CE
2
) input HIGH.
Data on the eight I/O pins (I/O
0
through I/O
7
) is then written
into the location specified on the address pins (A
0
through
A
16
).
Reading from the device is accomplished by taking Chip En-
able One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
),
an active HIGH Chip Enable (CE
2
), an active LOW Output En-
Logic Block Diagram
Pin Configurations
SOJ
Top View
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512 x 256 x 8
ARRAY
109–2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
109–3
I/O
3
I/O
4
I/O
5
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
109–1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low-Power Version
Shaded areas contain preliminary information.
7C109-10
7C1009-10
10
195
10
2
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 7, 1999
CY7C109
CY7C1009
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
−40°C
to +85°C
V
CC
5V
±
10%
5V
±
10%
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage .................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ......................................... 20 mA
[1]
Electrical Characteristics
Over the Operating Range
[3]
7C109-10
7C1009-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE
1
> V
CC
– 0.3V,
or CE
2
< 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
L
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
195
2.2
–0.3
–1
–5
Max.
7C109-12
7C1009-12
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
185
2.2
–0.3
–1
–5
Max.
7C109-15
7C1009-15
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
155
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
45
45
40
mA
I
SB2
10
2
10
2
10
2
mA
Shaded areas contain preliminary information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C109
CY7C1009
Electrical Characteristics
Over the Operating Range (continued)
7C109-20
7C1009-20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE
1
> V
CC
– 0.3V,
or CE
2
< 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
140
2.2
–0.3
–1
–5
Max.
7C109-25
7C1009-25
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
135
2.2
–0.3
–1
–5
Max.
7C109-35
7C1009-35
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
–300
125
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
30
30
25
mA
I
SB2
10
10
10
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
8
Unit
pF
pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 480Ω
R1 480Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤
3ns
3.0V
90%
10%
90%
10%
≤
3 ns
ALL INPUT PULSES
109–4
109–5
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
3
CY7C109
CY7C1009
Switching Characteristics
[3, 5]
Over the Operating Range
7C109-10
7C1009-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data
Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
CE
1
LOW to Power-Up, CE
2
HIGH to
Power-Up
CE
1
HIGH to Power-Down, CE
2
LOW to
Power-Down
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
10
8
8
0
0
8
6
0
3
5
0
10
3
5
0
12
0
5
3
6
0
15
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C109-12
7C1009-12
Min.
Max.
7C109-15
7C1009-15
Min.
Max.
Unit
WRITE CYCLE
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
12
10
10
0
0
10
7
0
3
6
15
12
12
0
0
12
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
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