LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with
16/32/64 kB RAM
Rev. 07 — 20 June 2008
Product data sheet
1. General description
The UART are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and
embedded trace support, together with 128 kB of embedded high speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options up to 64 kB, they are very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, PWM channels, and 32
GPIO lines make these microcontrollers particularly suitable for industrial control and
medical systems.
Remark:
Throughout the data sheet, the term LPC2104/2105/2106 will apply to devices
with and without /00 and /01 suffixes. Suffixes will be used to differentiate devices
whenever they include new features.
2. Features
2.1 New features implemented in LPC2104/2105/2106/01 devices
I
Fast GPIO port enables port pin toggling up to 3.5 times faster than the original device
and also allows for a port pin to be read at any time regardless of its function.
I
UART 0/1 include fractional baud rate generator, autobauding capabilities, and
handshake flow-control fully implemented in hardware.
I
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
I
SPI programmable data length and master mode enhancement.
I
Diversified Code Read Protection (CRP) enables different security levels to be
implemented.
I
General purpose timers can operate as external event counters.
2.2 Key common features
I
16/32-bit ARM7TDMI-S processor.
I
16/32/64 kB on-chip static RAM.
I
128 kB on-chip flash program memory. 128-bit-wide interface/accelerator enables high
speed 60 MHz operation.
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
I
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.
I
Vectored Interrupt Controller with configurable priorities and vector addresses.
I
EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service
routines can continue to execute whilst the foreground task is debugged with the
on-chip RealMonitor software.
I
Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
I
Multiple serial interfaces including two UARTs (16C550), Fast I
2
C-bus (400 kbit/s), and
SPI.
I
Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time
Clock and Watchdog.
I
Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 mm
×
7 mm)
package.
I
60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100
µs.
I
The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.
I
Two low power modes, Idle and Power-down.
I
Processor wake-up from Power-down mode via external interrupt.
I
Individual enable/disable of peripheral functions for power optimization.
I
Dual power supply:
N
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
±
8.3 %).
N
I/O power supply range of 3.0 V to 3.6 V (3.3 V
±
10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2104BBD48
LPC2104FBD48/00
LPC2104FBD48/01
LPC2105BBD48
LPC2105FBD48/00
LPC2105FBD48/01
LPC2106BBD48
LPC2106FBD48
LQFP48
LQFP48
LQFP48
LQFP48
LQFP48
LQFP48
LQFP48
LQFP48
Description
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
Version
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
Type number
LPC2104_2105_2106_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
2 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Ordering information
…continued
Package
Name
Description
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 48 leads;
body 7
×
7
×
1.4 mm
Version
SOT313-2
SOT313-2
SOT619-1
LQFP48
LQFP48
Table 1.
Type number
LPC2106FBD48/00
LPC2106FBD48/01
LPC2106FHN48
HVQFN48 plastic thermal enhanced very thin quad flat
package; no leads; 48 terminals; body
7
×
7
×
0.85 mm
HVQFN48 plastic thermal enhanced very thin quad flat
package; no leads; 48 terminals; body
7
×
7
×
0.85 mm
HVQFN48 plastic thermal enhanced very thin quad flat
package; no leads; 48 terminals; body
7
×
7
×
0.85 mm
LPC2106FHN48/00
SOT619-1
LPC2106FHN48/01
SOT619-1
3.1 Ordering options
Table 2.
Ordering options
Flash memory
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
128 kB
RAM
16 kB
16 kB
16 kB
32 kB
32 kB
32 kB
64 kB
64 kB
64 kB
64 kB
64 kB
64 kB
64 kB
Temperature range
0
°C
to +70
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
0
°C
to +70
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
0
°C
to +70
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
LPC2104BBD48
LPC2104FBD48/00
LPC2104FBD48/01
LPC2105BBD48
LPC2105FBD48/00
LPC2105FBD48/01
LPC2106BBD48
LPC2106FBD48
LPC2106FBD48/00
LPC2106FBD48/01
LPC2106FHN48
LPC2106FHN48/00
LPC2106FHN48/01
LPC2104_2105_2106_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
3 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4. Block diagram
TMS
(2)
TDI
(2)
RTCK
TRST
(2)
TCK
(2)
TDO
(2)
XTAL2
XTAL1
RESET
EMULATION
TRACE MODULE
LPC2104/2105/2106
TEST/DEBUG
INTERFACE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
ARM7TDMI-S
P0
V
DD(3V3)
V
DD(1V8)
V
SS
HIGH-SPEED
GPIO
(3)
32 PINS TOTAL
AHB BRIDGE
ARM7 LOCAL BUS
AMBA Advanced High-performance
Bus (AHB)
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
16/32/64 kB
SRAM
128 kB
FLASH
Advanced Peripheral
Bus (APB)
EINT[2:0]
(1)
EXTERNAL
INTERRUPTS
I
2
C-BUS SERIAL
INTERFACE
SCL
(1)
SDA
(1)
SCK
(1)
CAPTURE/
COMPARE
TIMER 0/TIMER 1
SPI/SSP
(3)
SERIAL INTERFACE
MOSI
(1)
MISO
(1)
SSEL
(1)
TXD[1:0]
(1)
RXD[1:0]
(1)
CAP0[2:0]
(1)
CAP1[3:0]
(1)
MAT0[2:0]
(1)
MAT1[3:0]
(1)
P0[31:0]
GENERAL
PURPOSE I/O
UART0/UART1
PWM[6:1]
(1)
PWM0
WATCHDOG
TIMER
DSR1
(1)
, CTS1
(1)
,
RTS1
(1)
, DTR1
(1)
,
DCD1
(1)
, RI1
(1)
REAL-TIME CLOCK
SYSTEM
CONTROL
002aaa412
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Available on LPC2104/2105/2106/01 only.
Fig 1.
Block diagram
LPC2104_2105_2106_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
4 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5. Pinning information
5.1 Pinning
46 P0.16/EINT0/MAT0.2
37 P0.12/DSR1/MAT1.0
36 P0.11/CTS1/CAP1.1
35 P0.10/RTS1/CAP1.0
34 P0.24/PIPESTAT1
33 P0.23/PIPESTAT0
32 P0.22/TRACECLK
31 V
SS
30 P0.9/RXD1/PWM6
29 P0.8/TXD1/PWM4
28 P0.7/SSEL/PWM2
27 DBGSEL
26 RTCK
25 n.c.
P0.0/TXD0/PWM1 13
P0.1/RXD0/PWM3 14
P0.30/TRACEPKT3/TDI 15
P0.31/EXTIN0/TDO 16
V
DD(3V3)
17
P0.2/SCL/CAP0.0 18
V
SS
19
n.c. 20
P0.3/SDA/MAT0.0 21
P0.4/SCK/CAP0.1 22
P0.5/MISO/MAT0.1 23
P0.6/MOSI/CAP0.2 24
002aaa411
41 P0.13/DTR1/MAT1.1
47 P0.17/CAP1.2/TRST
39 P0.26/TRACESYNC
48 P0.18/CAP1.3/TMS
44 P0.14/DCD1/EINT1
P0.19/MAT1.2/TCK
P0.20/MAT1.3/TDI
P0.21/PWM5/TDO
n.c.
V
DD(1V8)
RESET
V
SS
P0.27/TRACEPKT0/TRST
P0.28/TRACEPKT1/TMS
1
2
3
4
5
6
7
8
9
LPC2104/2105/2106
P0.29/TRACEPKT2/TCK 10
XTAL1 11
XTAL2 12
Pin configuration is identical for all LQFP48 packages.
Fig 2.
Pin configuration (LQFP48)
LPC2104_2105_2106_7
38 P0.25/PIPESTAT2
45 P0.15/RI1/EINT2
40 V
DD(3V3)
43 V
SS
42 n.c.
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
5 of 41
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