Data Path Interface (DPI) to
Utopia Level 2
Translation Device
IDT77V011
Single chip interface between multiple UTOPIA PHYs and a
single Data Path Interface (DPI).
Ideal for xDSL DSLAM and 25Mbps switching applications.
Supports ATM Forum UTOPIA Level 2 interface in both 8-bit
and 16-bit modes.
Supports UTOPIA Level 2 Cell Level Handshake.
Supports up to 31 PHYs on the UTOPIA Level 2 interface.
Supports either 4-bit or 8-bit DPI interface.
Supports cell sizes from 52 to 56 bytes on the DPI interface.
Supports DPI operation up to 50MHz.
Either Utility Bus or Parallel Manager Management interface
for configuring and reading status of PHY registers.
In-Stream™ (In-band) programming for configuration of
device and management interface communications.
TAG Routing for flexibility in routing cells.
Single +3.3V ± 0.3V power supply required.
Inputs are +5.0V tolerant.
By providing a smooth translation to the UTOPIA Level 2 multi-PHY
interface, the IDT77V011 offers the opportunity to connect up to 31 PHY
ports to a single 155Mbps port of the IDT77V400 Switching Memory.
The IDT77V011 can also provide both transmit and receive TAG
Routing, with each direction being individually programmed. In the
receive direction up to four bytes can be added to the cell. In the
transmit direction up to four bytes can be removed from the cell. This
makes the IDT77V011, when combined with the IDT77V400, an ideal
component for DSLAM and 25Mbps applications where the user would
like to implement OC-3 bandwidth of a single IDT77V400 port to a
number of lower bandwidth ports.
The 77V011 utilizes In-Stream™ programming for its device configu-
ration options. The cells are received on the DPI transmit interface, iden-
tified and sent to the internal cell interpreter for decoding and execution.
In-Stream™ programming cells are transmitted based on a round-robin
scheduler, which provides equal priority for each of the subports and the
cell generator. This methodology is also used to communicate and
configure the PHYs that are connected to the IDT77V011.
Other features include an EEPROM that holds information for initial-
ization and Discovery/Identify cells, and a Management interface to
access the PHY devices.
The IDT77V011provides the interface translation between a 4 or 8-bit
Data Path Interface (DPI) and an 8 or 16-bit UTOPIA Level 2 interface.
DPI offers a reduced device pin count and gives the IDT77V400
Switching Memory a high degree of port configuration flexibility.
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
QRLWSLUFVH'
QRLWSLUFVH'
QRLWSLUFVH'
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VHUXWDH)
VHUXWDH)
VHUXWDH)
VHUXWDH)
.
UTOPIA 2 8/16-bit
IDT77V011
DPI 4/8-bit
IDT77V400
Switching
Memory
.
ADSL
PHY
ADSL
PHY
ADSL
PHY
.
Management Bus
5348drw01
Figure 1 Typical IDT77011 ADSL DSLAM Application with the IDTV400 Switching Memory
1 of 43
2001 Integrated Device Technology, Inc.
March 15, 2001
DSC 4308/8
IDT77V011
INDEX
VCC
TxDATA[11]
TxDATA[10]
TxDATA[9]
TxDATA[8]
TxDATA[7]
TxDATA[6]
TxDATA[5]
GND
VCC
TxDATA[4]
TxDATA[3]
TxDATA[2]
TxDATA[1]
TxDATA[0]
TxREF
GND
VCC
DTxDATA[0]
DTxDATA[1]
DTxDATA[2]
DTxDATA[3]
DTxDATA[4]
DTxDATA[5]
DTxDATA[6]
DTxDATA[7]
DTxFRM
GND
DTxCLK
VCC
DRxCLK
DRxFRM
DRxDATA[0]
DRxDATA[1]
DRxDATA[2]
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GND
TxDATA[12]
TxDATA[13]
TxDATA[14]
TxDATA[15]
TxPRTY
T EN B
TxLED
VCC
GND
TSOC
TxADDR[4]
TxADDR[3]
TxADDR[2]
TxADDR[1]
TxADDR[0]
TCLK
GND
TCLAV
REFCLK
VCC
GND
RCLK
RENB
RxADDR[0]
RxADDR[1]
RxADDR[2]
RxADDR[3]
RxADDR[4]
RxLED
VCC
GND
RCLAV
RSOC
RxDATA[15]
VCC
VCC
DRxDATA[3]
DRxDATA[4]
DRxDATA[5]
DRxDATA[6]
DRxDATA[7]
VCC
GND
SYSCLK
S YSR ST
EEDIN
EEDOUT
EECS
EECLK
GND
CTRL_B
CTRL_A
VCC
MBUS[11]
MBUS[10]
MBUS[9]
MBUS[8]
MBUS[7]
MBUS[6]
MBUS[5]
GND
MBUS[4]
MBUS[3]
MBUS[2]
MBUS[1]
MBUS[0]
VCC
MGMT[4]
BMODE
PHYINT
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
DPI
Transmit
Interface
TAG & Port
Address
Removal
UTOPIA II
Transmit
Interface
Cell
Generator
EEPROM
Interface
Cell
Receiver
Management
Interface
DPI
Receive
Interface
TAG & Port
Address
Adder
UTOPIA II
Receive
Interface
5348drw02
IDT77V011
PQFP
TOP
VIEW
3
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
RxDATA[14]
RxDATA[13]
RxDATA[12]
RxDATA[11]
RxDATA[10]
RxDATA[9]
RxDATA[8]
VCC
GND
RxDATA[7]
RxDATA[6]
RxDATA[5]
RxDATA[4]
RxDATA[3]
RxDATA[2]
RxDATA[1]
RxDATA[0]
VCC
GND
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]
VCC
GND
MGMT[5]
MGMT[1]
MGMT[2]
MGMT[3]
PHY RST
VCC
5348drw03
1.
All power pins must be connected to a 3.3V ± 0.3V power supply.
2.
All GND pins must be connected to ground supply.
3.
This text does not indicate orientation of the actual part-marking.
2 of 43
March 15, 2001
IDT77V011
DTxDATA [0]
DTxDATA [1]
DTxDATA [2]
DTxDATA [3]
DTxDATA [4]
DTxDATA [5]
DTxDATA [6]
DTxDATA [7]
DTxFRM
DTxCLK
19
I
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0].
DPI Transmit Start of Frame Marker.
Transmit DPI Clock.
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0].
DPI Receive Start of Frame Marker.
Receive DPI Clock.
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
20
21
22
23
24
25
26
27
29
33
34
35
38
39
40
41
42
32
31
91
92
93
94
95
96
97
98
101
102
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I/O
I
I
I
I
I
I
I
I
I
I
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
DRxDATA [0]
DRxDATA [1]
DRxDATA [2]
DRxDATA [3]
DRxDATA [4]
DRxDATA [5]
DRxDATA [6]
DRxDATA [7]
DRxFRM
DRxCLK
RxDATA [0]
RxDATA [1]
RxDATA [2]
RxDATA [3]
RxDATA [4]
RxDATA [5]
RxDATA [6]
RxDATA [7]
RxDATA [8]
RxDATA [9]
3 of 43
QRLWSLUFVH'
March 15, 2001
SW
HGR0 WXXSX2 UHEPX1 HPD1 QL3
W Q,
QL3
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
IDT77V011
RxDATA [10]
103
I
Normal
Normal
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use
RxDATA [7:0].
UTOPIA 2 Receive Start of Cell marker.
UTOPIA 2 Receive Cell Available.
UTOPIA 2 Receive Enable.
UTOPIA 2 Receive Address Bus.
UTOPIA 2 Receive Address Bus.
UTOPIA 2 Receive Address Bus.
UTOPIA 2 Receive Address Bus.
UTOPIA 2 Receive Address Bus.
UTOPIA 2 Receive LED.
UTOPIA 2 Receive Clock.
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
RxDATA [11]
RxDATA [12]
RxDATA [13]
RxDATA [14]
RxDATA [15]
RSOC
RCLAV
RENB
RxADDR [0]
RxADDR [1]
RxADDR [2]
RxADDR [3]
RxADDR [4]
RxLED
RCLK
TxDATA [0]
TxDATA [1]
TxDATA [2]
TxDATA [3]
TxDATA [4]
TxDATA [5]
TxDATA [6]
TxDATA [7]
TxDATA [8]
TxDATA [9]
TxDATA [10]
104
105
106
107
110
111
112
121
120
119
118
117
116
115
122
15
14
13
12
11
8
7
6
5
4
3
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
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March 15, 2001
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IDT77V011
TxDATA [11]
TxDATA [12]
TxDATA [13]
TxDATA [14]
TxDATA [15]
TSOC
TCLAV
TENB
TxADDR[0]
2
O
Normal
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
UTOPIA 2 Transmit Start of Cell marker.
UTOPIA 2 Transmit Cell Available.
UTOPIA 2 Transmit Enable.
UTOPIA 2 Transmit Address Bus [LSB].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB].
UTOPIA 2 Transmit Address Bus [LSB+1].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB+1].
UTOPIA 2 Transmit Address Bus [LSB+2].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [MSB].
UTOPIA 2 Transmit Address Bus [LSB+3].
Initialize from EEPROM. Selects whether five bytes of EEPROM are to be written to In-Stream™ Cell
Header and In-Stream™ Subport. "0" do not write five byte value, "1" write five byte value from EEPROM.
UTOPIA 2 Transmit Address Bus [MSB].
UTOPIA 2 Transmit LED.
UTOPIA 2 Transmit Clock.
Parity for DTxDATA [15:0].
8 KHz reference clock used to generate TxREF.
8KHz reference clock used by PHY.
EEPROM Clock.
EEPROM Chip Select.
Serial Input from the EEPROM.
Serial Output to the EEPROM.
Bus Mode. Selects Motorola or Intel bus mode. "0" selects Motorola, "1" selects Intel.
143
142
141
140
134
126
138
129
O
O
O
O
O
I
O
O
I
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Reset
Normal
Reset
Normal
Reset
Normal
Reset
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
TxADDR[1]
130
O
I
TxADDR[2]
131
O
I
TxADDR[3]
132
O
I
TxADDR[4]
TxLED
TCLK
TxPRTY
REFCLK
TxREF
EECLK
EECS
EEDIN
EEDOUT
BMODE
MBUS[0]
133
137
128
139
125
16
50
49
47
48
70
67
O
O
O
O
I
O
O
O
I
O
I
O
UTOPIA 2 Address Bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[1]).
I
MBUS[1]
66
O
Reset
TxSIZE[0] - Number of bytes to remove from cell in transmit direction (LSB).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[2]).
I
Reset
TxSIZE[1] - number of bytes to remove from cell in transmit direction (LSB + 1).
5 of 43
QRLWSLUFVH'
March 15, 2001
SW
HGR0 WXXSX2 UHEPX1 HPD1 QL3
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QL3
PCB设计
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