DATA PATH INTERFACE (DPI)
TO UTOPIA LEVEL 2
TRANSLATION DEVICE
Features
x
x
x
x
x
x
PRELIMINARY
IDT77V011
x
x
x
Single chip interface between multiple UTOPIA PHYs and a single Data
Path Interface (DPI).
Ideal for xDSL DSLAM and 25Mbps switching applications.
Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16-
bit modes.
Supports UTOPIA Level 2 Cell Level Handshake.
Supports up to 31 PHYs on the UTOPIA Level 2 interface.
Supports either 4-bit or 8-bit DPI interface.
x
x
x
x
Supports cell sizes from 52 to 56 bytes on the DPI interface.
Supports DPI operation up to 50MHz.
Either Utility Bus or Parallel Manager Management interface for
configuring and reading status of PHY registers.
In-Stream™ (In-band) programming for configuration of device
and management interface communications.
TAG Routing for flexibility in routing cells.
Single +3.3V ± 0.3V power supply required.
Inputs are +5.0V tolerant.
.
UTOPIA 2 8/16-bit
IDT77V011
DPI 4/8-bit
IDT77V400
Switching
Memory
.
ADSL
PHY
ADSL
PHY
ADSL
PHY
.
Management Bus
5348drw01
Figure 1: Typical IDT77V011 ADSL DSLAM Application with the IDT77v400 Switching Mmory.
Description
The IDT77V011provides the interface translation between a 4 or 8-
bit Data Path Interface (DPI) and an 8 or 16-bit UTOPIA Level 2 interface.
DPI offers a reduced device pin count and gives the IDT77V400 Switching
Memory a high degree of port configuration flexibility.
By providing a smooth translation to the UTOPIA Level 2 multi-PHY
interface, the IDT77V011 offers the opportunity to connect up to 31 PHY
ports to a single 155Mbps port of the IDT77V400 Switching Memory.
The IDT77V011 can also provide both transmit and receive TAG
Routing, with each direction being individually programmed. In the
receive direction up to four bytes can be added to the cell. In the
transmit direction up to four bytes can be removed from the cell. This
makes the IDT77V011, when combined with the IDT77V400, an
ideal component for DSLAM and 25Mbps applications where the
user would like to implement OC-3 bandwidth of a single IDT77V400
port to a number of lower bandwidth ports.
The 77V011 utilizes In-Stream™ programming for its device
configuration options. The cells are received on the DPI transmit
interface, indentified and sent to the internal cell interpreter for
decoding and execution. In-Stream™ programming cells are trans-
mitted based on a round-robin scheduler, which provides equal
priority for each of the subports and the cell generator. This method-
ology is also used to communicate and configure the PHYs that are
connected to the IDT77V011.
Other features include an EEPROM that holds information for initializa-
tion and Discovery/Identify cells, and a Management interface to access
the PHY devices.
SPETEMBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC -/1
IDT77V011
Data Path Interface (DPI) to UTOPIA Level II Header Translation Device
Preliminary
Industrial Temperature Range
Block Diagram
DPI
Transmit
Interface
TAG & Port
Address
Removal
UTOPIA II
Transmit
Interface
EEPROM
Interface
Cell
Generator
Cell
Receiver
Management
Interface
DPI
Receive
Interface
TAG & Port
Address
Adder
UTOPIA II
Receive
Interface
5348drw02
.
2
IDT77V011
Data Path Interface (DPI) to UTOPIA Level II Header Translation Device
Preliminary
Industrial Temperature Range
Pin Configuration
GND
TxDATA[12]
TxDATA[13]
TxDATA[14]
TxDATA[15]
TxPRTY
TENB
TxLED
VCC
GND
TSOC
TxADDR[4]
TxADDR[3]
TxADDR[2]
TxADDR[1]
TxADDR[0]
TCLK
GND
TCLAV
REFCLK
VCC
GND
RCLK
RENB
RxADDR[0]
RxADDR[1]
RxADDR[2]
RxADDR[3]
RxADDR[4]
RxLED
VCC
GND
RCLAV
RSOC
RxDATA[15]
VCC
INDEX
VCC
TxDATA[11]
TxDATA[10]
TxDATA[9]
TxDATA[8]
TxDATA[7]
TxDATA[6]
TxDATA[5]
GND
VCC
TxDATA[4]
TxDATA[3]
TxDATA[2]
TxDATA[1]
TxDATA[0]
TxREF
GND
VCC
DTxDATA[0]
DTxDATA[1]
DTxDATA[2]
DTxDATA[3]
DTxDATA[4]
DTxDATA[5]
DTxDATA[6]
DTxDATA[7]
DTxFRM
GND
DTxCLK
VCC
DRxCLK
DRxFRM
DRxDATA[0]
DRxDATA[1]
DRxDATA[2]
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
IDT77V011
PQFP
TOP
VIEW
(3)
VCC
DRxDATA[3]
DRxDATA[4]
DRxDATA[5]
DRxDATA[6]
DRxDATA[7]
VCC
GND
SYSCLK
SYSRST
EEDIN
EEDOUT
EECS
EECLK
GND
CTRL_A
CTRL_B
VCC
MBUS[11]
MBUS[10]
MBUS[9]
MBUS[8]
MBUS[7]
MBUS[6]
MBUS[5]
GND
MBUS[4]
MBUS[3]
MBUS[2]
MBUS[1]
MBUS[0]
VCC
MGMT[4]
BMODE
PHYINT
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
RxDATA[14]
RxDATA[13]
RxDATA[12]
RxDATA[11]
RxDATA[10]
RxDATA[9]
RxDATA[8]
VCC
GND
RxDATA[7]
RxDATA[6]
RxDATA[5]
RxDATA[4]
RxDATA[3]
RxDATA[2]
RxDATA[1]
RxDATA[0]
VCC
GND
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]
VCC
GND
MGMT[5]
MGMT[1]
MGMT[2]
MGMT[3]
PHYRST
VCC
5348drw03
NOTES:
1. All power pins must be connected to a 3.3V ± 0.3V power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
3
6.42
IDT77V011
Data Path Interface (DPI) to UTOPIA Level II Header Translation Device
Preliminary
Industrial Temperature Range
Pin Definitions
Pin N am e
D T xD ATA [0 ]
D T xD ATA [1 ]
D T xD ATA [2 ]
D T xD ATA [3 ]
D T xD ATA [4 ]
D T xD ATA [5 ]
D T xD ATA [6 ]
D T xD ATA [7 ]
D T xF R M
D T xC L K
D R xD ATA [ 0 ]
D R xD ATA [ 1 ]
D R xD ATA [ 2 ]
D R xD ATA [ 3 ]
D R xD ATA [ 4 ]
D R xD ATA [ 5 ]
D R xD ATA [ 6 ]
D R xD ATA [ 7 ]
D R xF R M
D R xC L K
R xD ATA [ 0 ]
R xD ATA [ 1 ]
R xD ATA [ 2 ]
R xD ATA [ 3 ]
R xD ATA [ 4 ]
R xD ATA [ 5 ]
R xD ATA [ 6 ]
R xD ATA [ 7 ]
R xD ATA [ 8 ]
R xD ATA [ 9 ]
R xD ATA [1 0 ]
P in
N u m b er
19
20
21
22
23
24
25
26
27
29
33
34
35
38
39
40
41
42
32
31
91
92
93
94
95
96
97
98
101
102
103
In p u t/
O u tp u t
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I /O
I
I
I
I
I
I
I
I
I
I
I
M ode
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
No rm a l
D e scrip tio n
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
4 -b it o r 8 -b it inp ut d a t a b us us e d to t ra ns fe r d a ta f ro m a D P I d e vic e .
W he n in 4 -b it m o d e us e D T xD ATA [ 3 : 0 ] .
D P I Tra ns m it S t a rt o f F r a m e M a rk e r.
Tra ns m it D P I C lo c k .
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
4 -b it o r 8 -b it o ut p ut d a ta b us us e d to tr a ns fe r d a ta t o a D P I d e vic e . W he n
in 4 -b it m o d e us e D R xD ATA [ 3 : 0 ].
D P I R e c e ive S t a rt o f F r a m e M a rk e r.
R e c e ive D P I C lo c k .
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
8 -b it o r 1 6 - b it UT O P IA 2 inp ut d a t a b us us e d t o tra n s fe r d a t a f ro m a P HY
d e vic e . W he n in 8 -b it m o d e us e R xD ATA [7 :0 ].
5 3 4 8 tb l0 1
4
IDT77V011
Data Path Interface (DPI) to UTOPIA Level II Header Translation Device
Preliminary
Industrial Temperature Range
Pin Definitions (con't.)
Pin N am e
R xD ATA [11]
R xD ATA [12]
R xD ATA [13]
R xD ATA [14]
R xD ATA [15]
RSO C
R C LAV
RENB
R xA D D R [0]
R xA D D R [1]
R xA D D R [2]
R xA D D R [3]
R xA D D R [4]
RxLED
R C LK
T xD ATA [0]
T xD ATA [1]
T xD ATA [2]
T xD ATA [3]
T xD ATA [4]
T xD ATA [5]
T xD ATA [6]
T xD ATA [7]
T xD ATA [8]
T xD ATA [9]
T xD ATA [10]
T xD ATA [11]
T xD ATA [12]
T xD ATA [13]
T xD ATA [14]
T xD ATA [15]
TSO C
T C LAV
TENB
P in
N u m ber
10 4
10 5
10 6
10 7
110
111
112
12 1
12 0
119
118
117
116
115
12 2
15
14
13
12
11
8
7
6
5
4
3
2
14 3
14 2
14 1
14 0
13 4
12 6
13 8
Input/
O utput
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
M ode
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
Norm al
D e scription
8- bit or 1 6-bit UT O P IA 2 input data bus us ed to tra ns fer da ta from a P HY
de vic e. W hen in 8-bit m od e use R xD ATA [7:0].
8- bit or 1 6-bit UT O P IA 2 input data bus us ed to tra ns fer da ta from a P HY
de vic e. W hen in 8-bit m od e use R xD ATA [7:0].
8- bit or 1 6-bit UT O P IA 2 input data bus us ed to tra ns fer da ta from a P HY
de vic e. W hen in 8-bit m od e use R xD ATA [7:0].
8- bit or 1 6-bit UT O P IA 2 input data bus us ed to tra ns fer da ta from a P HY
de vic e. W hen in 8-bit m od e use R xD ATA [7:0].
8- bit or 1 6-bit UT O P IA 2 input data bus us ed to tra ns fer da ta from a P HY
de vic e. W hen in 8-bit m od e use R xD ATA [7:0].
UTO P IA 2 R e ce ive S ta rt of C ell m ark er.
UT O P IA 2 R ec eive C ell A vailable.
UT O P IA 2 R ec eive E na ble.
UTO P IA 2 R ec eive A dd res s B us .
UTO P IA 2 R ec eive A dd res s B us .
UTO P IA 2 R ec eive A dd res s B us .
UTO P IA 2 R ec eive A dd res s B us .
UTO P IA 2 R ec eive A dd res s B us .
UT O P IA 2 R ec eive L E D .
UTO P IA 2 R ec eive C loc k .
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
8-b it or 16 -bit UT O P IA 2 outp ut d ata bus us ed to tr a ns fer d ata to a P HY
de vic e. W hen in 8-bit m o de use T xD ATA [7:0].
UTO P IA 2 Trans m it S ta rt of C ell m ark er.
UT O P IA 2 Tr a ns m it Ce ll A vaila ble.
UT O P IA 2 Trans m it E na ble.
53 48tb l02
5
6.42
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
