Intel
®
Xeon
™
Processor
at 1.40 GHz, 1.50 GHz, 1.70 GHz and 2 GHz
Datasheet
Product Features
s
s
s
s
s
s
s
s
s
Available at 1.40, 1.50, 1.70 and 2 GHz
Dual processing server/workstation support
Binary compatible with applications
running on previous members of the Intel
microprocessor line
Intel
®
NetBurst™ micro-architecture
System bus frequency at 400 MHz
— Bandwidth up to 3.2 Gbytes/sec
Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor
core frequency
Hyper Pipelined Technology
Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency
from main execution loops
— Includes 8 KB Level 1 data cache
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s
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256 KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache) with 8-way
associativity and Error Correcting Code
(ECC)
Enables system support of up to 64 GB of
physical memory
144 new Streaming SIMD Extensions 2
(SSE2) instructions
Enhanced floating point and multimedia
unit for enhanced video, audio, encryption,
and 3D performance
Power Management capabilities
— System Management mode
— Multiple low-power states
Advanced System Management Features
— Processor Information ROM (PIROM)
— OEM Scratch EEPROM
— Machine Check Architecture (MCA)
The Intel
®
Xeon™ processor is designed for high-performance workstation and server
applications. Based on the new Intel
®
NetBurst™ micro-architecture, it is binary compatible
with previous Intel Architecture processors. The Intel Xeon processor is scalable to two
processors in a multiprocessor system providing exceptional performance for applications
running on advanced operating systems such as Windows* XP, Windows 2000 and UNIX*. The
Intel Xeon processor extends the power of the Intel
®
Pentium
®
III
Xeon™ processor with new
features designed to make this processor the right choice for powerful workstation, advanced
servers, and mission-critical applications. Advanced features simplify system management and
meet the needs of a robust IT environment, resulting in maximized system up time, convenient
system management, and optimal configuration.
Order Number: 249665-002
September 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
Copyright © Intel Corporation, 2001
* Other names and brands may be claimed as the property of others.
Datasheet
Contents
Contents
1.0
Introduction
.....................................................................................................................................9
1.1
Terminology .......................................................................................................................10
1.1.1
Processor Packaging Terminology ......................................................................10
1.2
State of Data ......................................................................................................................11
1.3
References.........................................................................................................................11
Electrical Specifications
................................................................................................................13
2.1
System Bus and GTLREF..................................................................................................13
2.2
Power and Ground Pins.....................................................................................................13
2.3
Decoupling Guidelines .......................................................................................................13
2.3.1
VCC Decoupling ..................................................................................................14
2.3.2
System Bus AGTL+ Decoupling ..........................................................................14
2.4
System Bus Clock (BCLK[1:0]) and Processor Clocking ...................................................14
2.4.1
Phase Lock Loop (PLL) Power and Filter ............................................................15
2.4.2
System Bus to Core Frequency Ratios ...............................................................16
2.4.3
Mixing Processors ...............................................................................................17
2.5
Voltage Identification.........................................................................................................17
2.5.1
Mixing Processors of Different Voltages..............................................................18
2.6
Reserved Or Unused Pins .................................................................................................19
2.7
System Bus Signal Groups ................................................................................................19
2.8
Asynchronous GTL+ Signals .............................................................................................21
2.9
Test Access Port (TAP) Connection ..................................................................................21
2.10
Maximum Ratings ..............................................................................................................21
2.11
Processor DC Specifications .............................................................................................22
2.12
AGTL+ System Bus Specifications ....................................................................................27
2.13
System Bus AC Specifications...........................................................................................27
2.14
Processor AC Timing Waveforms ......................................................................................32
System Bus Signal Quality Specifications
..................................................................................39
3.1
System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines ............................................................................................39
3.2
System Bus Signal Quality Specifications and Measurement Guidelines..........................40
3.2.1
Ringback Guidelines............................................................................................40
3.2.2
Overshoot/Undershoot Guidelines ......................................................................43
3.2.3
Overshoot/Undershoot Magnitude.......................................................................43
3.2.4
Overshoot/Undershoot Pulse Duration ................................................................43
3.2.5
Activity Factor ......................................................................................................43
3.2.6
Reading Overshoot/Undershoot Specification Tables .........................................44
3.2.7
Determining if a System Meets the Overshoot/Undershoot
Specifications ......................................................................................................44
Mechanical Specifications.............................................................................................................49
4.1
Processor Mechanical Specifications ................................................................................50
4.2
Package Load Specifications .............................................................................................54
4.3
Insertion Specifications ......................................................................................................55
4.4
Mass Specifications ...........................................................................................................55
4.5
Processor Materials ...........................................................................................................55
4.6
Processor Markings ...........................................................................................................56
4.7
Pin-Out Diagrams ..............................................................................................................57
Pin Listing and Signal Definitions
................................................................................................59
5.1
Processor Pin Assignments ...............................................................................................59
5.1.1
Pin Listing by Pin Name ......................................................................................59
5.1.2
Pin Listing by Pin Number ...................................................................................68
5.2
Signal Definitions ...............................................................................................................77
Thermal Specifications
..................................................................................................................87
6.1
Thermal Specifications.......................................................................................................87
6.2
Thermal Analysis ...............................................................................................................88
6.2.1
Processor Case Temperature Measurement ......................................................88
2.0
3.0
4.0
5.0
6.0
Datasheet
3
Contents
7.0
Features..........................................................................................................................................
89
7.1
Power-On Configuration Options ...................................................................................... 89
7.2
Clock Control and Low Power States................................................................................ 89
7.2.1
Normal State—State 1........................................................................................ 89
7.2.2
AutoHALT Powerdown State—State 2 ............................................................... 90
7.2.3
Stop-Grant State—State 3.................................................................................. 90
7.2.4
HALT/Grant Snoop State—State 4..................................................................... 91
7.2.5
Sleep State—State 5 .......................................................................................... 91
7.2.6
Bus Response During Low Power States........................................................... 92
7.3
Thermal Monitor ................................................................................................................ 92
7.3.1
Thermal Diode .................................................................................................... 93
7.4
System Management Bus (SMBus) Interface ................................................................... 93
7.4.1
Processor Information ROM (PIROM) ................................................................ 94
7.4.2
Scratch EEPROM ............................................................................................... 97
7.4.3
PIROM and Scratch EEPROM Supported SMBus Transactions ....................... 97
7.4.4
SMBus Thermal Sensor...................................................................................... 97
7.4.5
Thermal Sensor Supported SMBus Transactions .............................................. 98
7.4.6
SMBus Thermal Sensor Registers ................................................................... 100
7.4.7
SMBus Thermal Sensor Alert Interrupt............................................................. 102
7.4.8
SMBus Device Addressing ............................................................................... 103
Boxed Processor Specifications................................................................................................
105
8.1
Introduction ..................................................................................................................... 105
8.2
Mechanical Specifications............................................................................................... 106
8.2.1
Boxed Processor Heatsink Dimensions............................................................ 106
8.2.2
Boxed Processor Heatsink Weight ................................................................... 106
8.2.3
Boxed Processor Retention Mechanism and Heatsink Supports ..................... 106
8.3
Boxed Processor Requirements ..................................................................................... 109
8.3.1
Processor Wind Tunnel .................................................................................... 109
8.3.2
Fan Power Supply ............................................................................................ 109
8.4
Thermal Specifications.................................................................................................... 112
8.4.1
Boxed Processor Cooling Requirements.......................................................... 112
Debug Tools Specifications
....................................................................................................... 113
9.1
Debug Port System Requirements.................................................................................. 113
9.2
Target System Implementation ....................................................................................... 114
9.2.1
System Implementation .................................................................................... 114
9.3
Logic Analyzer Interface (LAI)........................................................................................ 114
9.3.1
Mechanical Considerations............................................................................... 114
9.3.2
Electrical Considerations .................................................................................. 114
Processor Core Frequency Determination................................................................................
115
8.0
9.0
10.0
4
Datasheet
Contents
Figures
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2
3
4
5
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10
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13
14
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31
32
30
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32
33
34
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36
37
38
39
40
41
Typical VCCIOPLL, VCCA and VSSA Power Distribution .................................................15
Phase Lock Loop (PLL) Filter Requirements .....................................................................16
Electrical Test Circuit .........................................................................................................32
TCK Clock Waveform ........................................................................................................33
Differential Clock Waveform ..............................................................................................33
System Bus Common Clock Valid Delay Timing Waveform ..............................................34
System Bus Source Synchronous 2X (Address) Timing Waveform ..................................34
System Bus Source Synchronous 4X (Data) Timing Waveform ........................................35
System Bus Reset and Configuration Timing Waveform ...................................................36
Power-On Reset and Configuration Timing Waveform ......................................................36
TAP Valid Delay Timing Waveform....................................................................................37
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform..................37
THERMTRIP# Power Down Waveform .............................................................................37
SMBus Timing Waveform ..................................................................................................38
SMBus Valid Delay Timing Waveform ...............................................................................38
BCLK[1:0] Signal Integrity Waveform ................................................................................40
Low-to-High Receiver Ringback Tolerance for AGTL+ and Async GTL+ Signals .............41
High-to-Low Receiver Ringback Tolerance for AGTL+ and Async GTL+ Signals .............41
Low-to-High Receiver Ringback Tolerance for TAP Buffers ..............................................42
High-to-Low Receiver Ringback Tolerance for TAP Buffers ..............................................42
Maximum Acceptable Overshoot/Undershoot Waveform ..................................................47
Processor Assembly Drawing (Including Socket) ..............................................................49
Top View Component Placement Detail ............................................................................50
Processor Package Drawing..............................................................................................51
Top View - Component Height Keep-in .............................................................................52
Processor Cross Section View - Pin Side Component Keep-in .........................................52
Processor Pin Detail ..........................................................................................................53
IHS Flatness and Tilt Drawing ...........................................................................................54
Processor Top-Side Markings............................................................................................56
Processor Bottom-Side Markings ......................................................................................56
Processor Pin-out Diagram -- Top View ............................................................................57
Processor Pin-out Diagram -- Bottom View .......................................................................58
Processor with Thermal and Mechanical Components - Exploded View...........................87
Thermocouple Placement for Case Temperature (TCASE) Measurement........................88
Stop Clock State Machine..................................................................................................90
Logical Schematic of SMBus Circuitry ...............................................................................94
Mechanical Representation of the Boxed Processor Passive Heatsink .........................105
Boxed Processor Retention Mechanism and Clip............................................................107
Multiple View Space Requirements for the Boxed Processor..........................................108
Boxed Processor Fan Power Cable Connector Description ............................................110
Processor Wind Tunnel Dimensions ................................................................................111
Boxed Processor Heatsink Airflow Direction....................................................................112
Timing Diagram of the Clock Ratio Signals .....................................................................115
Example Schematic for Clock Ratio Pin Sharing .............................................................116
Datasheet
5
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