IC71V08F32xS04
IC71V16F32xS04
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package (MCP) -
32 Mbit Simultaneous Operation Flash Memory and 4 Mbit Static RAM
MCP FEATURES
• Power supply voltage 2.7V to 3.3V
• High performance:
Flash: 85ns maximum access time
SRAM: 70ns maximum access time
• Package:
64 and 73-ball BGA - 32 Mbit Flash/4 Mbit SRAM
• Operating Temperature: -25
o
C to +85
o
C
• Operating supply voltage: 2.7 to 3.3V
• Power supply current (Active mode)
- Read: 16mA (MAX.)
- Program/ Erase: 30mA (MAX.)
• Standby current: 5 µA (MAX.)
• Operating ambient temperature: -25 to +85
o
C
• Program/ erase time
- Program 9.0 µs/ byte (TYP.)
11.0 µs/ word (TYP.)
- Sector erase: 0.7s (TYP.)
• Number of program/ erase: 1,000,000 times (MIN)
FLASH FEATURES
• Two bank organization enabling simultaneous execution
of erase/ program and read
• Bank organization: 2 banks (16 Mbits + 16 Mbits)
• Memory organization: 4,194,304 words x 8 bits (BYTE
mode)
2,097,152 words x 16 bits (WORD
mode)
• Sector organization: 71 sectors (8 Kbytes/ 4 Kwords x 8
sectors, 64 Kbytes/ 32 Kwords x 63 sectors)
• Bottom boot sector organization
- Boot sector allocated to the lowest address (sector)
• 3-state output
• Automatic program
- Program suspend/ resume
• Unlock bypass program
• Automatic erase
- Chip erase
- Sector erase (sectors can be combined freely)
- Erase suspend/ resume
• Program/ Erase completion detection
- Detection through data polling and toggle bits
- Detection through RY/BY pin
• Sector group protection
- Any sector group can be protected
- Any protected sector group can be temporary unpro-
tected
• Sectors can be used for boot application
• Hardware reset and standby using
RESET
pin
• Automatic sleep mode
• Boot block sector protect by
WP/ACC
pin
• Conforms to common flash memory interface (CFI)
• Extra One Time Protect Sector provided
• Access time: 85ns (MAX.)
SRAM FEATURES (4 Mb density)
• Low Power Dissipation:
Operating: 45 mA maximum
Standby: 3.3V 10 µA maximum
3.0V 5 µA maximum
• Chip Selects:
CE1s,
CE2s
• Power down feature using
CE1s
, or CE2s
• Data retention supply voltage: 1.5 to 3.3 volt
• Byte data control:
LBs
(DQ0-DQ7),
UB
s (DQ8-DQ15) -
on x16 version
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 32 Mbit Flash/4 Mbit
SRAM having a data bus of either x8 or x16. The 32 Mbit flash
is composed of 2,097,152 words of 16 bits or 4,194,304 bytes
of 4 bits. Data lines DQ0-DQ7 handle the x8 format, while
lines DQ0-DQ15 handle the x16 format.
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V
supply, or can be programmed in a standard EPROM
programmer.
The 32 Mbit flash/4 Mbit SRAM is offered in a 64-pin BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 85 ns and
the SRAM access time is 70ns.
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized perfor-
mance can be achieved by first initializing a program or
erase function in one bank, then immediately starting a read
from the other bank. Both operations would then be operat-
ing simultaneously, with zero latency.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
MCP002-0A 7/11/2003
ARM技术
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