Datasheet
IS-1715ARH, IS-1715AEH
Radiation Hardened Complementary Switch FET Drivers
The radiation hardened
IS-1715ARH
and
IS-1715AEH
are high speed, high current,
complementary power FET drivers designed for use
in synchronous rectification circuits. Soft switching
transitions for the two output waveforms can be
managed by setting the independently programmable
delays. Alternatively, the delay pins can be configured
for zero-voltage sensing to allow for precise switching
control.
The IS-1715ARH and IS-1715AEH have a single
input, which is PWM and TTL compatible, and can run
at frequencies up to 1MHz. The AUX output switches
immediately at the rising edge of the INPUT, but waits
for the T2 delay before responding to the falling edge.
A logic low on the enable pin (ENBL) places both
outputs into an active-low mode, and an Undervoltage
Lockout (UVLO) function is set at 9V (maximum).
These devices are constructed with the dielectrically
isolated Rad Hard Silicon Gate (RSG) process and
are immune to Single Event Latch-Up (SEL). They
have been specifically designed to provide highly
reliable performance in harsh radiation environments.
Features
• Electrically screened to SMD #5962-00521
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
○ Gamma dose 3x10
5
rad(Si)
○ Latch-up immune
• PWR output current (source and sink): 3A (peak)
• AUX output current (source and sink): 3A (peak)
• Low operating supply current: 6mA (max)
• Wide programmable delay range: 100ns to 600ns
• Configurable for zero-voltage switching
• Switching frequency to 1MHz
• Both outputs active-low in Sleep mode
• 9V (maximum) UVLO
Related Literature
For a full list of related documents, visit our website:
•
IS-1715ARH, IS-1715AEH
device pages
Applications
• Synchronous rectification in power supplies
VCC
600
VCC = 10V
VCC
PWM
IS-1715
INPUT
VCC
T1
T2
ENBL
PWR
AUX
GND
100
R
T
1
GND
R
T
2
0
0
10
20
30
40
125 °C
T2
50
R
T
(kΩ)
25 °C
T2
60
70
-55 °C
T2
80
90
100
Delay (ns)
500
400
300
200
T1
T1
T1
125 °C
25 °C
-55 °C
PWM
Controller
GND
Figure 1. IS-1715 Typical Application Diagram
Figure 2. T1 Delay, T2 Delay vs R
T
vs Temperature
FN4875 Rev.3.00
Aug.16.19
Page 1 of 12
IS-1715ARH, IS-1715AEH
1. Overview
1.
1.1
Overview
Functional Block Diagram
IN Driver Out
PWR
INPUT
InputESD
IN
OUT
EN
Out
IDEL
VARDELFALL
VIN
Out
IDEL
VARDELFALL
VIN
3V_REF
VOUT
EN
IN Driver Out
AUX
T1
T2
InputESD
InputESD
EN
IOFF
IDOFF
IDON
ION
VREF
VARDELBIAS
ENABLE
InputESD
IN
OUT
UVDET
UV
Note: VCC and VSS (GND) connections not shown.
Figure 3. Functional Block Diagram
FN4875 Rev.3.00
Aug.16.19
Page 2 of 12
IS-1715ARH, IS-1715AEH
1. Overview
1.2
Ordering Information
Ordering SMD Number
(Note
1)
Part Number
(Note
2)
IS9-1715ARH-Q
IS9-1715ARH-8
IS9-1715ARH-T
IS0-1715ARH-Q
IS0-1715ARH/SAMPLE (Note
3)
IS9-1715ARH/PROTO (Note
3)
IS9-1715AEH-Q
IS0-1715AEH-Q
Temp. Range
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Package
(RoHS Compliant)
16 Ld Flatpack
16 Ld Flatpack
16 Ld Flatpack
Die
Die
16 Ld Flatpack
16 Ld Flatpack
Die
Pkg. Dwg. #
K16.A
K16.A
K16.A
N/A
N/A
K16.A
K16.A
N/A
5962F0052101VXC
5962F0052101QXC
5962R0052101TXC
5962F0052101V9A
N/A
N/A
5962F0052103VXC
5962F0052103V9A
Notes:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers
listed must be used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are
intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature
range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the
electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive 100% screening
across the temperature range to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because
there is no radiation assurance testing and they are not DLA qualified devices.
1.3
Pin Configuration
IS-1715ARH, IS-1715AEH
Flatpack (CDFP4-F16)
Top View
NC
V
CC
PWR
V
SS
V
SS
AUX
NC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ENBL
T1
INPUT
V
SS
V
SS
T2
V
CC
NC
1.4
Pin Description
Pin Name
NC
V
CC
PWR
No connection.
Chip positive supply (10V to 18V).
Output. PWR switches immediately (neglecting propagation delay) at INPUT’s falling edge but is
delayed after the rising edge by the value of the resistance on T1. PWR is capable of sinking and
sourcing 3.0A of peak gate drive current. During sleep mode, PWR is active low.
Chip negative supply (ground connection).
Output. AUX switches immediately (neglecting propagation delay) at INPUT’s rising edge but is
delayed after the falling edge before switching by the value of the resistance on T2. AUX is capable
of sinking and sourcing 3.0A of peak gate drive current. During sleep mode, AUX is active low.
Input. A resistor to ground programs the time delay between PWR switch turn-off and AUX turn-on.
Description
Pin Number
1, 7, 8, 9
2, 10
3
4, 5, 12,13
6
V
SS
AUX
11
T2
FN4875 Rev.3.00
Aug.16.19
Page 3 of 12
IS-1715ARH, IS-1715AEH
Pin Number
14
Pin Name
INPUT
Description
1. Overview
Input. INPUT switches at TTL logic levels but the allowable range is from 0V to VCC, allowing direct
connection to most common IC PWM controller outputs. The rising edge immediately switches the
AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the
INPUT falling edge immediately turns off the PWR output and initiates a timing delay, T2, before
switching the AUX output.
Input. A resistor to ground programs the time delay between AXU switch turn-off and PWR turn-on.
Input. The ENABLE input switches at TTL logic levels, but the allowable range is from 0 to VCC. The
ENABLE input places the device into sleep mode when it is a logic low. The current into VCC during
sleep mode is typically 500µA.
15
16
T1
ENBL
FN4875 Rev.3.00
Aug.16.19
Page 4 of 12
IS-1715ARH, IS-1715AEH
2. Specifications
2.
2.1
Specifications
Absolute Maximum Ratings
Parameter
Minimum
10
0
Maximum
20
VCC
Unit
VDC
VDC
Supply Voltage Range (VCC)
DC Input Voltage Range (INPUT, ENBL)
CAUTION:
Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
90
θ
JC
(°C/W)
18
16 Ld FP Package (Notes
4, 5)
Notes:
4. θ
JA
is measured with the component mounted to a high effective thermal conductivity test board in free air. See
TB379
for details.
5. For θ
JC
, the “case temp” location is the center of the ceramic on the package underside.
Parameter
Lead Temperature (soldering, 10 seconds)
Maximum Junction Temperature (T
JMAX
)
Storage Temperature Range
-65
Minimum
Maximum
+265
+175
+150
Unit
°C
°C
°C
2.3
Recommended Operating Conditions
Parameter
Minimum
10
-55
Maximum
18
+125
Unit
VDC
°C
Supply Voltage Range (VCC)
Temperature Range
2.4
Electrical Specifications
Typ
Max
Min
(Note
6)
(Note
6)
V
CC
= 10V to 18V, ENBL ≥ 3V, Limits apply over the operating temperature range, -55°C to +125°C unless otherwise specified.
Description
Overall
Operating Voltage Range
Input Current, Nominal
Input Current, Sleep Mode
Under Voltage, Rising Threshold
Under Voltage, Falling Threshold
Under Voltage Delta
Power Driver (PWR)
Pre Turn-On PWR Output, Low
PWR Pin Output Low, Saturation
V
PPWR
V
PWR
V
CC
= 0V, ENBL ≤ 0.8V, I
OUT
= 10mA
INPUT = 0.8V, I
OUT
= 40mA
INPUT = 0.8V, I
OUT
= 100mA
PWR Pin Output High, Saturation
V
CC -
V
PWR
INPUT = 3.0V, I
OUT
= -40mA
INPUT = 3.0V, I
OUT
= -100mA
Rise Time
t
RP
C
L
= 2200pF
-
-
-
-
-
15
-
-
-
-
-
-
2.0
1.0
1.5
1.0
1.5
50
V
V
V
V
V
ns
V
CC
I
CC
I
CCS
UV+
UV-
UVD
ENBL = 3.0V
ENBL = 0.8V
10
1.0
300
8.5
7.7
0
-
-
-
-
-
-
18
6.0
900
9.5
8.8
2.0
V
mA
µA
V
V
V
Parameter
Test Conditions
Unit
FN4875 Rev.3.00
Aug.16.19
Page 5 of 12
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