CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage (Note 2)
V
SUPPLY
=
±5V,
R
L
= 100Ω, Unless Otherwise Specified
TEST CONDITIONS
TEMP (°C)
MIN
TYP
MAX
UNITS
25
Full
-
-
-
39
35
-
-
-
-
25
-
8
-
10
45
-
14
51
10
-
50
2
25
35
-
-
-
-
-
40
65
-
-
mV
mV
µV/°C
dB
dB
nV/√Hz
pA/√Hz
µA
µA
kΩ
pF
Output Offset Voltage Drift
PSRR
Full
25
Full
Input Noise Voltage (Note 2)
Input Noise Current (Note 2)
Input Bias Current (Note 2)
100kHz
100kHz
25
25
25
Full
Input Resistance
Input Capacitance
TRANSFER CHARACTERISTICS
Gain
V
OUT
= 2V
P-P
±2V
Full Scale
25
25
25
Full
0.980
0.975
-
0.990
-
0.003
1.02
1.025
-
V/V
V/V
%
±V
±V
mA
mA
±V
mA
mA
DC Non-Linearity (Note 2)
OUTPUT CHARACTERISTICS
Output Voltage (Note 2)
25
25
Full
3.0
2.5
50
35
3.3
3.0
60
50
-
-
-
-
Output Current (Note 2)
R
L
= 50Ω
25, 85
-40
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Supply Current (Note 2)
Full
25
Full
AC CHARACTERISTICS
-3dB Bandwidth (Note 2)
Slew Rate
Full Power Bandwidth (Note 2)
Gain Flatness (Note 2)
V
OUT
= 0.2V
P-P
V
OUT
= 5V
P-P
V
OUT
= 4V
P-P
To 100MHz
To 30MHz
Linear Phase Deviation (Note 2)
2nd Harmonic Distortion (Note 2)
3rd Harmonic Distortion (Note 2)
3rd Order Intercept (Note 2)
DC to 100MHz
50MHz, V
OUT
= 2V
P-P
50MHz, V
OUT
= 2V
P-P
100MHz
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
750
1300
150
±
0.03
±
0.01
±
0.3
4.5
-
-
-
21
-
5.5
26
33
-
-
-
-
-
-
-
-
-
MHz
V/µs
MHz
dB
dB
°
dBc
dBc
dBm
-60
-80
30
2
FN2944.8
June 6, 2006
HFA1110
Electrical Specifications
PARAMETER
-1dB Gain Compression
Reverse Gain (S
12
, Note 2)
TRANSIENT RESPONSE
Rise Time
Overshoot (Note 2)
0.2% Settling Time (Note 2)
0.1% Settling Time (Note 2)
Overdrive Recovery Time
Differential Gain
Differential Phase
NOTE:
2. See Typical Performance Curves for more information.
3.58MHz, R
L
= 75Ω
3.58MHz, R
L
= 75Ω
V
OUT
= 0.5V Step
V
OUT
= 1.0V Step, Input Signal
Rise/Fall = 1ns
V
OUT
= 1V to 0V
V
OUT
= 1V to 0V
25
25
25
25
25
25
25
-
-
-
-
-
-
-
0.5
2.5
7
11
15
0.04
0.025
-
-
-
-
-
-
-
ns
%
ns
ns
ns
%
°
V
SUPPLY
=
±5V,
R
L
= 100Ω, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
100MHz
100MHz, V
OUT
= 1V
P-P
TEMP (°C)
25
25
MIN
-
-
TYP
14
-60
MAX
-
-
UNITS
dBm
dB
Application Information
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
S
) in series with the output.
See the “Recommended R
S
vs Load Capacitance” graph for
specific recommendations.
An example of a good high frequency layout is the
Evaluation Board shown below.
50Ω
+5V
0.1µF
10µF
1
2
3
IN
50Ω
4
HFA1110
8
7
6
5
10µF
-5V
0.1µF
R
S
OUT
SCHEMATIC DIAGRAM
BOTTOM LAYOUT
Evaluation Board
An evaluation board is available for the HFA1110 (part
number HFA1110EVAL). Please contact your local sales
office for information.
The layout and schematic of the board are shown here:
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
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