ispLSI
®
1032 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
ispLSI 1032-60LT
ispLSI 1032-80LT
ispLSI 1032-90LT
ispLSI 1032-60LTI
ispLSI 1032-60LJ
ispLSI 1032-80LJ
ispLSI 1032-90LJ
ispLSI 1032-60LJI
ispLSI 1016-60LH/883
5962-9476201MXC
Product Status
Reference PCN
ispLSI 1032
Discontinued
PCN#13-10
PCN#05A-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421
Phone (503) 268-8000
FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispLSI 1032
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 90 MHz Maximum Operating Frequency
—
f
max
= 60 MHz for Industrial and Military/883 Devices
—
t
pd
= 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
®
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
C7
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Output Routing Pool
A2
A3
A4
A5
A6
A7
Logic
Array
D Q
C5
C4
C3
C2
C1
C0
D Q
GLB
D Q
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
1032_08
1
Output Routing Pool
A1
D Q
C6
Specifications
ispLSI 1032
Functional Block Diagram
Figure 1. ispLSI 1032 Functional Block Diagram
I/O I/O I/O I/O
63 62 61 60
RESET
I/O I/O I/O I/O
59 58 57 56
I/O I/O I/O I/O
55 54 53 52
I/O I/O I/O I/O
51 50 49 48
IN IN
7 6
Input Bus
Generic
Logic Blocks
(GLBs)
D7
D6
Output Routing Pool (ORP)
D5
D4
D3
D2
D1
D0
IN 5
IN 4
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
C7
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
A0
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
C6
C5
C4
C3
C2
C1
C0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
Input Bus
Global
Routing
Pool
(GRP)
B0
B1
B2
B3
B4
B5
B6
B7
Megablock
Output Routing Pool (ORP)
Input Bus
Clock
Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
ispEN
SDO/IN 2
SCLK/IN 3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y Y Y Y
0 1 2 3
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control. Additionally, all outputs are polarity se-
lectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032 device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1032 device contains four
of these Megablocks.
2
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
0139(1)-32-isp
Specifications
ispLSI 1032
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
4.75
4.5
4.5
0
MAX.
5.25
5.5
5.5
0.8
Commercial
T
A
= 0°C to +70°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
UNITS
V
CC
V
IL
V
IH
Supply Voltage
Industrial
T
A
= -40°C to +85°C
V
Military/883
T
C
= -55°C to +125°C
Input Low Voltage
V
V
Input High Voltage
2.0
Vcc
+ 1
Table 2- 0005Aisp w/mil.eps
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
1
MAXIMUM
UNITS
pf
TEST CONDITIONS
V
CC
=5.0V, V
IN
=2.0V
C
1
C
2
Dedicated Input Capacitance
Commercial/Industrial
8
Military
10
pf
V
CC
=5.0V, V
IN
=2.0V
I/O and Clock Capacitance
10
pf
V
CC
=5.0V, V
I/O
, V
Y
=2.0V
Table 2- 0006
1
.
Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER
MINIMUM
20
10000
MAXIMUM
—
—
UNITS
Years
Data Retention
Erase/Reprogram Cycles
Cycles
Table 2- 0008B
3
Specifications
ispLSI 1032
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤
3ns 10% to 90%
1.5V
1.5V
See figure 2
Figure 2. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Table 2- 0003
3-state levels are measured 0.5V from steady-state
active level.
Output Load Conditions (see figure 2)
Test Condition
A
R1
*
CL includes Test Fixture and Probe Capacitance.
R2
CL
470Ω
390Ω
390Ω
390Ω
35pF
35pF
35pF
5pF
B
Active High
∞
∞
Active Low
470Ω
C
Active High to Z
at
V
OH
- 0.5V
at
V
OL
+ 0.5V
390Ω
Active Low to Z
470Ω
390Ω
5pF
DC Electrical Characteristics
Over Recommended Operating Conditions
CONDITION
SYMBOL
PARAMETER
MIN.
–
–
–
–
–
–
–
–
TYP.
3
–
–
–
–
–
–
–
MAX.
0.4
–
UNITS
V
V
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
Output Low Voltage
I
OL
=8 mA
Output High Voltage
I
OH
=-4 mA
2.4
Input or I/O Low Leakage Current 0V
≤
V
IN
≤
V
IL
(MAX.)
Input or I/O High Leakage Current 3.5V
≤
V
IN
≤
V
CC
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
(MAX.)
-10
10
μA
μA
μA
μA
mA
mA
mA
-150
-150
-200
190
220
V
CC
= 5V, V
OUT
= 0.5V
f
TOGGLE
= 1 MHz
I
CC
2,4
Operating Power Supply Current
V
IL
= 0.5V, V
IH
= 3.0V Commercial
130
135
Industrial/Military
1.
2.
3.
4.
One output at a time for a maximum duration of one second.
Measured using eight 16-bit counters.
Typical values are at V
CC
= 5V and T
A
= 25
o
C.
Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I
CC
.
Table 2- 0007A-32-isp
4
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