PUSB3F4-TBR
10
ESD protection for ultra high-speed interfaces
Rev. 1 — 6 October 2011
Product data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as High-Definition
Multimedia Interface (HDMI), DisplayPort, SuperSpeed USB, external Serial Advanced
Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces
against ElectroStatic Discharge (ESD).
The device includes high-level ESD protection diodes for ultra high-speed signal lines and
is encapsulated in a 4-channel XSON10 Pb-free package.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.5 pF. These diodes provide protection to downstream components
from ESD voltages up to
8
kV contact according to IEC 61000-4-2, level 4.
XS
ON
1.2 Features and benefits
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
System ESD protection for USB 2.0 and USB SuperSpeed 3.0, HDMI 1.3 and
HDMI 1.4, DisplayPort, eSATA and LVDS
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of
8
kV according to IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with
0.05 pF matching capacitance between signal pairs
Line capacitance of only 0.5 pF for each channel
4-channel, XSON10 Pb-free package
Design-friendly ’pass-thru’ signal routing
1.3 Applications
The device is designed for high-speed receiver and transmitter port protection:
TVs, monitors
DVD recorders and players
Notebooks, mother boards, graphic cards and ports
Set-top boxes and game consoles
NXP Semiconductors
PUSB3F4-TBR
ESD protection for ultra high-speed interfaces
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
7
8
9
10
Pinning
Description
channel 1 ESD protection
channel 2 ESD protection
ground
channel 3 ESD protection
channel 4 ESD protection
not connected
not connected
ground
not connected
not connected
1
2
3
4
5
Transparent top view
10
9
8
7
6
1
2
4
5
Symbol
CH1
CH2
GND
CH3
CH4
n.c.
n.c.
GND
n.c.
n.c.
Simplified outline
Graphic symbol
XSON10
3, 8
018aaa001
3. Ordering information
Table 2.
Ordering information
Package
Name
PUSB3F4-TBR
XSON10
Description
plastic extremely thin small outline package;
no leads; 10 terminals; body 1
2.5
0.5 mm
Version
SOT1176-1
Type number
4. Marking
Table 3.
Marking codes
Marking code
F4
Type number
PUSB3F4-TBR
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
I
V
ESD
Parameter
input voltage
electrostatic discharge
voltage
IEC 61000-4-2, level 4
contact discharge
air discharge
T
amb
T
stg
[1]
[1]
Conditions
Min
0.5
-
-
40
55
Max
+5.5
8
15
+85
+125
Unit
V
kV
kV
C
C
ambient temperature
storage temperature
All pins to ground.
PUSB3F4-TBR
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 October 2011
2 of 14
NXP Semiconductors
PUSB3F4-TBR
ESD protection for ultra high-speed interfaces
6. Characteristics
Table 5.
Characteristics
T
amb
= 25
C unless otherwise specified.
Symbol
V
BRzd
I
LRzd
V
F
C
ch(TMDS)
C
ch(TMDS)
C
ch(mutual)
R
dyn
Parameter
Zener diode
breakdown voltage
Zener diode reverse
leakage current
forward voltage
TMDS channel
capacitance
TMDS channel
capacitance difference
mutual channel
capacitance
dynamic resistance
f = 1 MHz;
V
bias
= 2.5 V
f = 1 MHz;
V
bias
= 2.5 V
f = 1 MHz;
V
bias
= 2.5 V
I=1A
positive transient
negative transient
V
CL(ch)trt(pos)
positive transient channel V
ESD
= 8 kV
clamping voltage
[1]
[2]
[3]
[4]
This parameter is guaranteed by design.
Between signal pin and pin n.c.
According to IEC 61000-4-5 and IEC 61000-4-9.
Human Body Model (HBM) according to JESD22-A-J114D.
[4]
[1]
Conditions
I
test
= 1 mA
per TMDS channel;
V
I
= 3.0 V
Min
6
-
-
0.4
-
-
Typ
-
-
0.7
0.5
0.05
0.07
Max
9
1
-
0.7
-
-
Unit
V
A
V
pF
pF
pF
[1]
[1][2]
[3]
-
-
-
1
1
8
-
-
-
V
PUSB3F4-TBR
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 October 2011
3 of 14
NXP Semiconductors
PUSB3F4-TBR
ESD protection for ultra high-speed interfaces
3
Sdd21;
Scc21
(dB)
−3
018aaa002
0
Sdd21;
NEXT
(dB)
−30
018aaa003
(1)
(2)
−9
−60
−15
10
6
10
7
10
8
10
9
f (Hz)
10
10
−90
10
8
10
9
f (Hz)
10
10
(1) Sdd21
(2) Scc21
Normalized to 100
;
differential pairs at CH1/CH2 or at CH3/CH4
Sdd21
Normalized to 100
;
differential pairs CH1/CH2 versus CH3/CH4
Fig 1.
Mixed-mode differential and common-mode
insertion loss; typical values
Fig 2.
Mixed-mode differential NEXT crosstalk;
typical values
PUSB3F4-TBR
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 October 2011
4 of 14
NXP Semiconductors
PUSB3F4-TBR
ESD protection for ultra high-speed interfaces
018aaa004
018aaa005
5 Gbit/s; USB 3.0 CP0 pattern
5 Gbit/s; USB 3.0 CP0 pattern
Fig 3.
Eye diagram using reference PCB
0.4
C
d
(pF)
0.2
Fig 4.
Typical eye diagram for PUSB3F4-TBR
018aaa006
(1)
0.0
(2)
−0.2
−0.4
−0.5
1.5
3.5
V
bias
(V)
5.5
(1) Pin 2
(2) Pin 1
Deviation from typical capacitance normalized at V
bias
= 2.5 V
Fig 5.
Line capacitance as a function of bias voltage; typical values
PUSB3F4-TBR
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 6 October 2011
5 of 14
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
