74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Rev. 3 — 11 September 2013
Product data sheet
1. General description
The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The
device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial
output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded
into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When
PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of
CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH
transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which
enable the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standard no. 7A
Input levels:
For 74HC166: CMOS level
For 74HCT166: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC166N
74HCT166N
74HC166D
74HCT166D
74HC166DB
74HCT166DB
74HC166PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT338-1
SOT403-1
40 C
to +125
C
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
40 C
to +125
C
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number Package
NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
4. Functional diagram
15
PE
2
3
4
5
10
11
12
14
9
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
7
CE
6
aaa-008816
aaa-008817
1
SRG8
DS
6
7
15
9
≥1
M2
R
C1/2
1
2
3
Q7
13
4
5
10
11
12
14
2,1D
2,1D
2,1D
13
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
2
D0
15
1
PE
DS
3
D1
4
D2
5
D3
10
D4
11
D5
12
D6
14
D7
9
7
6
MR
CP
CE
8-BIT PARALLEL/SERIAL-IN/
SERIAL-OUT SHIFT REGISTER
Q7
13
aaa-008818
Fig 3.
Functional diagram
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
2 of 21
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Product data sheet
Rev. 3 — 11 September 2013
3 of 21
74HC_HCT166
NXP Semiconductors
D0
D1
D2
D3
D4
D5
D6
D7
PE
DS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
CP
CE
S
CP
FF
1
S
CP
FF
2
S
CP
FF
3
S
CP
FF
4
S
CP
FF
5
S
CP
FF
6
S
CP
FF
7
S
CP
FF
8
R RD
R RD
R RD
R RD
R RD
R RD
R RD
R RD
MR
Q7
aaa-008819
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 4.
Logic diagram
NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
74HC166
74HCT166
DS
D0
D1
D2
D3
CE
CP
GND
1
2
3
4
5
6
7
8
aaa-008815
16 V
CC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
9
MR
Fig 5.
Pin configuration (DIP16, SO16 and (T)SSOP16)
5.2 Pin description
Table 2.
Symbol
DS
D0 to D7
CE
CP
GND
MR
Q7
PE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 10, 11, 12, 14
6
7
8
9
13
15
16
Description
serial data input
parallel data inputs
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
4 of 21
NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
6. Functional description
Table 3.
Function table
[1]
Inputs
PE
parallel load
serial shift
hold “do nothing”
[1]
Operating modes
Qn registers
CE
I
I
I
I
H
CP
X
DS
X
X
l
h
X
D0 to D7
I
h
X
X
X
Q0
L
H
L
H
q0
Q1 to Q6
L to L
H to H
q0 to q5
q0 to q5
q1 to q6
Output
Q7
L
H
q6
q6
q7
I
I
h
h
X
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
CP
mode
control
inputs
CE
MR
DS
shift/
load
D0
D1
D2
D3
parallel
inputs
D4
D5
D6
D7
output
Q7
serial shift
inhibit
clear
load
aaa-008820
H
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
serial shift
Fig 6.
Typical clear, shift, load, inhibit, and shift sequences
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
5 of 21
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