Low Skew, 1-to-24 Differential-to-
LVCMOS/LVTTL Fanout Buffer
Data Sheet
8344I
G
ENERAL
D
ESCRIPTION
The 8344I is a low voltage, low skew fanout buffer and a member
of the family of High Performance Clock Solutions from IDT. The
8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1,
nCLK1 pairs can accept most standard differential input levels.
The 8344I is designed to translate any differential signal levels
to LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48
by utilizing the ability of the outputs to drive two series terminated
lines. Redundant clock applications can make use of the dual clock
input. The dual clock inputs also facilitate board level testing. 8344I
is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
8344I ideal for those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
•
Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
•
Two selectable differential clock input pairs for redundant
clock applications
•
CLKx, nCLKx pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 100MHz
•
Translates any single-ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
•
Multiple output enable pins for disabling unused outputs
in reduced fanout applications
•
Output skew: 275ps (maximum)
•
Part-to-part skew: 600ps (maximum)
•
Bank skew: 150ps (maximum)
•
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
48-Lead LQFP
6
7mm x 7mm x 1.4mm pack-
7
age body
8
Y Package
9
Top View
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
8344I
36
35
34
33
32
31
30
29
28
27
26
25
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
OE1
OE2
OE3
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
©2015 Integrated Device Technology, Inc
1
December 14, 2015
8344I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 5, 6
7, 8, 11, 12
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
13
15, 19
16
17
20
21
22
Name
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
V
DDO
GND
CLK_SEL
V
DD
nCLK1
CLK1
nCLK0
CLK0
OE3
Type
Output
Power
Power
Input
Power
Input
Input
Input
Input
Input
Pullup
Pullup
Description
Single-ended LVCMOS/LVTTL outputs.
7Ω typical output impedance.
Output supply pins.
Power supply ground.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0.
LVTTL / LVCMOS interface levels.
Positive supply pins.
Inverting differential clock input.
Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pullup
Output enable. Controls enabling and disabling of outputs
Q16 through Q23. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs
23
OE2
Input
Pullup
Q8 through Q15. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs
24
OE1
Input
Pullup
Q0 through Q7. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL outputs.
25, 26, 29, 30
Q0, Q1, Q2, Q3
Output
7Ω typical output impedance.
31, 32, 35, 36
Q4, Q5, Q6, Q7
Single-ended LVCMOS/LVTTL outputs.
37, 38, 41, 42
Q8, Q9, Q10, Q11
Output
7Ω typical output impedance.
43, 44, 47, 48 Q12, Q13, Q14, Q15
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
51
51
7
Test Conditions
Minimum
Typical
4
20
Maximum
Units
pF
pF
kΩ
kΩ
Ω
©2015 Integrated Device Technology, Inc
2
December 14, 2015
8344I Data Sheet
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Bank 1
Input
OE1
0
1
Output
Q0-Q7
Hi-Z
Enabled
Input
OE2
0
1
Bank 2
Output
Q8-Q15
Hi-Z
Enabled
Input
OE3
0
1
Bank 3
Output
Q16-Q23
Hi-Z
Enabled
T
ABLE
3B. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
CLK0, nCLK0
Selected
De-selected
Clock
CLK1, nCLK1
De-selected
Selected
T
ABLE
3C. C
LOCK
I
NPUTS
F
UNCTION
T
ABLE
Inputs
OE1, OE2, OE3
1
1
1
1
1
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q0 thru Q23
LOW
HIGH
LOW
HIGH
HIGH
LOW
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section on page 13, Figure 8, which discusses wiring the differential input
to accept single ended levels.
©2015 Integrated Device Technology, Inc
3
December 14, 2015
8344I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
95
Units
V
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
95
Units
V
V
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
95
Units
V
V
mA
©2015 Integrated Device Technology, Inc
4
December 14, 2015
8344I Data Sheet
T
ABLE
4D. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
OE1, OE2, OE3
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.465, V
IN
= 0V
V
DD
= V
DDO
= 3.135V
I
OH
= -36mA
V
DD
= V
DDO
= 3.135V
I
OL
= 36mA
-150
-5
2.6
0.6
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.8
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
T
ABLE
4E. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
OE1, OE2, OE3
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.465, V
IN
= 0
V
DD
= 3.135V,
V
DDO
= 2.375V
I
OH
= -27mA
V
DD
= 3.135V,
V
DDO
= 2.365V
I
OL
= 27mA
-150
-5
2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.8
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
Output High Voltage
V
OL
Output Low Voltage
0.63
V
T
ABLE
4F. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
OE1, OE2, OE3
CLK_SEL
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625, V
IN
= 0V
V
DD
= 2.625, V
IN
= 0V
V
DD
= VDDO = 2.375V
I
OH
= -27mA
V
DD
= VDDO = 2.375V
I
OL
= 27mA
-150
-5
2
0.6
Test Conditions
Minimum
2
-0.3
Typical
Maximum
2.9
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
©2015 Integrated Device Technology, Inc
5
December 14, 2015
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