DATASHEET
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
Description
The ICS557-08 is a 2:1 multiplexer chip that allows the user
to select one of the two HCSL (Host Clock Signal Level)
input pairs and fans out to one pair of differential HCSL or
LVDS outputs. This chip is suited especially for
PCI-Express applications, where there is a need to select
the PCI-Express clock either locally from the PCI-E card or
from the motherboard.
ICS557-08
Features
•
•
•
•
•
•
Packaged in 16-pin TSSOP
Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input clock frequency of up to 200 MHz
For PCIe Gen2/3 applications, see the 5V41068A
Block Diagram
VDD
3
OE
IN1
IN1
IN2
IN2
MUX
2 to 1
CLK
CLK
3
SEL
GND
PD
Rr (IREF)
IDT®
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
1
ICS557-08
REV L 112111
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Pin Assignment
VDD
IN1
IN1
PD
IN2
IN2
OE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL
CLK
CLK
GND
GND
VDD
VDD
IREF
Select Table
SEL
0
1
Input Pair Selected
IN2/ IN2
IN1/ IN1
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
VDD
IN1
IN1
PD
IN2
IN2
OE
GND
IREF
VDD
VDD
GND
GND
CLK
CLK
SEL
Pin Type
Power
Input
Input
Input
Input
Input
Input
Power
Output
Power
Power
Power
Power
Output
Output
Input
Pin Description
Connect to +3.3 V. Supply voltage for Input clocks.
HCSL true input signal 1.
HCSL complimentary input signal 1.
Powers down the chip and tri-states outputs when low. Internal pull-up
HCSL true input signal 2.
HCSL complimentary input signal 2.
Provides output or, tri-states output (High = enable outputs; Low = disable).
Internal pull-up resistor.
Connect to ground.
Precision resistor attached to this pin is connected to the internal current
Connect to +3.3 V. Supply Voltage for Output Clocks.
Connect to +3.3 V. Supply Voltage for Output Clocks.
Connect to ground.
Connect to ground.
HCSL/LVDS Complimentary output clock .
HCSL/LVDS True output clock.
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
IDT®
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
2
ICS557-08
REV L 112111
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-08 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01
μF
should
be connected between VDD and GND pins as close to the
device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50Ω then Rr = 475Ω
,
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-08.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
Load Resistors R
L
Since the clock outputs are open source outputs, 50Ω
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-08
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-08 can also be configured for LVDS compatible
voltage levels. See the
LVDS Compatible Layout
Guidelines
section.
IDT®
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
3
ICS557-08
REV L 112111
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
Output Structures
IREF
=2.3 mA
6*IREF
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-08.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT®
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
4
ICS557-08
REV L 112111
ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
PCIE MULTIPLEXER
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
R
S
R
T
Differential Routing on a Single PCB
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Differential Routing to a PCI Express Connector
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
inch
ohm
ohm
Unit
inch
inch
Unit
inch
inch
PCI-Express Device Routing
L1
R
S
L1’
R
S
L2
L4
L4’
R
T
L3’
R
T
L3
L2’
ICS557-08
Output
Clock
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
t
OR
500 ps
500 ps
t
OF
0.525 V
0.175 V
0.525 V
0.175 V
IDT®
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS GEN1
5
ICS557-08
REV L 112111
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