MOTOROLA
SEMICONDUCTOR
TECHNICAL
DATA
M u Iti-Character
lED
CMOS
The MC144898 is a flexible light-emitting-diode
driver which directly in-
terfaces to individual lamps, 7-segment displays, or various combinations of
both. LEOs wired with common cathodes are driven in a multiplexed-by-5
fashion. Communication with an MCUIMPU is established through a synchro-
nous serial port. The MC 144898 features data retention plus decode and scan
circuitry, thus relieving processor overhead. A single, current-setting resistor
is the only ancillary component required.
A single device can drive anyone of the following: a 5-digit display plus
decimals, a 4-112-digit display plus decimals and sign, or 25 lamps. A special
technique allows driving 5 112 digits; see Figure 16. A configuration register
allows the drive capability to be partitioned off to suit many additional applica-
tions. The on-chip decoder outputs 7-segment-format
numerals O to 9, hexa-
decimal characters A to F, plus 151etters and symbols.
The MC144898 is compatible with the Motorola SPI and National MI-
CRO-WIRETM serial data ports. The chip's patented 8itGrabberTM registers
augment the serial interface by allowing random access without steering or
address bits. A 24-bit transfer updates the display register. Changing the con-
figuration register requires an 8-bit transfer.
.Operating
Voltage Range of Drive Circuitry: 4.5 to 5.5 V
.Operating
Junction Temperature Range: -40° to 130°C
.Current Sources Controlled by Single Resistor Provide Anode Drive
.Low-Resistance
FET Switches Provide Direct Common Cathode Interface
.Low-Power
Mode (Extinguishes the LEDs) and Brightness Controlled via
Serial Port
.Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI
in Low-Power Mode
.Power-On
Reset (POR) Blanks the Display on Power-Up, Independent of
Supply Ramp Up Time
.May Be Used with Double-Heterojunction
LEDs for Optimum Efficiency
.Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.)
MC14489B
Driver
p SVFFiX
PLASTICOIP
CASE73$
Display/lamp
PW SUFF,~
SOOPACKAGE "
CASE 7510
..
ORDERING
MC14489BP
MC14489BDW
INFQRMATJON
PlaSticDtP
SOOP~gec
BitGrabber is a trademark of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor
Corp.
REVO
November
2000
BLOCK DIAGRAM
12
D
C
10
4
24–1/2–STAGE
SHIFT REGISTER
4
4
4
4
4
PIN 3 = VDD
PIN 14 = VSS
18
DATA IN
CLOCK
11
DATA OUT
ENABLE
BitGrabber
CONFIGURATION REGISTER
8 BITS
BitGrabber
DISPLAY REGISTER
24 BITS
4
4
4
4
4
4
POR
OSCILLATOR AND
CONTROL LOGIC
5
5
NIBBLE MUX AND
DECODER ROM
7 a TO g
h
DIM/BRIGHT
8
BLANK
BANK SWITCHES (FETs)
9
13
15
16
17
BANK 1 BANK 2 BANK 3 BANK 4 BANK 5
7
a
ANODE DRIVERS
(CURRENT SOURCES)
6
b
5 4 2 1 20 19
c d e f g h
Rx
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Symbol
VDD
Vin
Parameter
Value
Unit
V
V
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 6.0
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
15
Vout
Iin
DC Output Voltage
DC Input Current — per Pin
(Includes Pin 8)
mA
mA
Iout
DC Output Current —
Pins 1, 2, 4 – 7, 19, 20 Sourcing
Sinking
Pins 9, 13, 15, 16, 17 Sinking
– 40
10
320
Pin 18
±
15
IDD, ISS
TJ
DC Supply Current, VDD and VSS Pins
Chip Junction Temperature
±
350
mA
°C
– 40 to + 130
R
θJA
Device Thermal Resistance,
Junction–to–Ambient (see Thermal
Considerations section)
Plastic DIP
SOG Package
Storage Temperature
°C/W
90
100
Tstg
TL
– 65 to + 150
260
°C
°C
Lead Temperature, 1 mm from Case for
10 Seconds
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and Vout should be constrained to the range
VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
MC14489B
2
MOTOROLA
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TJ = – 40° to 130°C* unless otherwise indicated)
Symbol
VDD
VDD (stby)
Parameter
Power Supply Voltage Range of LED Drive Circuitry
Minimum Standby Voltage
Bits Retained in Display and
Configuration Registers, Data
Port Fully Functional
Test Condition
VDD
V
—
—
Guaranteed
Limit
4.5 to 5.5
3.0
Unit
V
V
VIL
VIH
VHys
VOL
Maximum Low–Level Input Voltage
(Data In, Clock, Enable)
Minimum High–Level Input Voltage
(Data In, Clock, Enable)
Minimum Hysteresis Voltage
(Data In, Clock, Enable)
Maximum Low–Level Output Voltage
(Data Out)
Iout = 20
µA
Iout = 1.3 mA
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
4.5
3.0
5.5
4.5
5.5
5.5
4.5
5.0
5.0
5.5
5.5
5.5
5.0
5.5
0.9
1.65
2.1
3.85
0.2
0.4
0.1
0.1
0.4
2.9
5.4
4.1
±
2.0
±
0.1
0.2
13 to 17.5
6 to 9
50
1
1
10
100
V
V
V
V
VOH
Minimum High–Level Output Voltage
(Data Out)
Iout = – 20
µA
Iout = – 800
µA
V
Iin
Maximum Input Leakage Current
(Data In Clock Enable)
In, Clock,
Vin = VDD or VSS
Vin = VDD or VSS,
TJ = 25°C only
Vout = 1.0 V
Rx = 2.0 kΩ, Vout = 3.0 V,
Dimmer Bit = High
Rx = 2.0 kΩ, Vout = 3.0 V,
Dimmer Bit = Low
µA
iOL
iOH
Minimum Sinking Current
(a, b, c, d, e, f, g, h)
Peak Sourcing Current — See Figure 7 for currents up to
35 mA (a, b, c, d, e, f, g, h)
mA
mA
IOZ
Maximum Output Leakage Current
(Bank 1 Bank 2 Bank 3 Bank 4 Bank 5)
1,
2,
3,
4,
Vout = VDD (FET Leakage)
Vout = VDD (FET Leakage),
TJ = 25°C only
Vout = VSS (Protection Diode
Leakage)
µA
Ron
IDD, ISS
Maximum ON Resistance
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
Maximum Quiescent Supply Current
Iout = 0 to 200 mA
Device in Low–Power Mode,
Vin = VSS or VDD, Rx in
Place, Outputs Open
Same as Above, TJ = 25°C
Ω
µA
5.5
5.5
20
1.5
mA
Iss
Maximum RMS Operating Supply Current
(The VSS leg does not contain the Rx current component.
See Pin Descriptions.)
Device NOT in Low–Power
Mode, Vin = VSS or VDD,
Outputs Open
* See Thermal Considerations section.
MOTOROLA
MC14489B
3
AC ELECTRICAL CHARACTERISTICS
(TJ = – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns)
Symbol
fclk
Parameter
Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock tw below
(Figure 1)
Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5)
Maximum Output Transistion Time, Data Out
(Figures 1 and 5)
Refresh Rate — Bank 1 through Bank 5
(Figures 2 and 6)
Maximum Input Capacitance — Data In, Clock, Enable
VDD
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
—
Guaranteed
Limit
dc to 3.0
dc to 4.0
dc to 4.0
140
80
80
70
50
50
NA
700 to 1900
700 to 1900
10
Unit
MHz
tPLH,
tPHL
tTLH,
tTHL
fR
ns
ns
Hz
Cin
pF
* See Thermal Considerations section.
TIMING REQUIREMENTS
(TJ = – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated
)
Symbol
tsu, th
Parameter
Minimum Setup and Hold Times, Data In versus Clock
(Figure 3)
Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4)
Minimum Active–Low Pulse Width, Enable
(Figure 4)
Minimum Inactive–High Pulse Width, Enable
(Figure 4)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1)
VDD
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Guaranteed
Limit
50
40
40
150
100
100
4.5
3.4
3.4
300
150
150
167
125
125
1
1
1
Unit
ns
tsu, th,
trec
tw(L)
ns
µs
tw(H)
ns
tw
ns
tr, tf
ms
* See Thermal Considerations section.
** For a high–speed 8–Clock access, th for Enable is determined as follows:
VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 – (7500/fclk)
VDD = 4.5 to 5.5 V, f > 2.34 MHz: th = 3300 – (7500/fclk)
clk
where th is in ns and fclk is in MHz.
NOTES:
1. This restriction does NOT apply for fclk rates less than those listed above. For “slow” fclk rates, use the th limits in the above table.
2. This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
MC14489B
4
MOTOROLA
tf
90%
CLOCK 50%
10%
tw
1/fclk
tPLH
DATA OUT
90%
50%
10%
tTLH
tr
VDD
VSS
tw
tPHL
BANK
OUTPUT
tTHL
50%
1/fR
Figure 1.
Figure 2.
tw(L)
VALID
VDD
DATA IN
50%
VSS
tsu
CLOCK
th
50%
VSS
VDD
CLOCK
tsu
th
ENABLE
50%
tw(H)
VDD
VSS
trec
VDD
50%
FIRST
CLOCK
LAST
CLOCK
VSS
Figure 3.
Figure 4.
VDD
TEST POINT
TEST POINT
56
Ω
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL
*
CL
*
*
Includes all probe and fixture capacitance.
Figure 5.
*
Includes all probe and fixture capacitance.
Figure 6.
MOTOROLA
MC14489B
5
嵌入式系统
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