L
OW
S
KEW
,
÷
1/÷2
÷
D
IFFERENTIAL
-
TO
- 3.3V LVPECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8737-11 is a low skew, high performance
Differential-to-3.3V LVPECL Clock Generator/Divider. The
ICS8737-11 has two selectable clock inputs. The CLK, nCLK
pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels.The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
ICS8737-11
F
EATURES
•
2 divide by 1 differential 3.3V LVPECL outputs;
2 divide by 2 differential 3.3V LVPECL outputs
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 650MHz
•
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•
Output skew: 60ps (maximum)
•
Part-to-part skew: 200ps (maximum)
•
Bank skew: Bank A - 20ps (maximum),
Bank B - 35ps (maximum)
•
Additive phase jitter, RMS: 0.04ps (typical)
•
Propagation delay: 1.7ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Lead-Free package RoHS compliant
B
LOCK
D
IAGRAM
QA0
nQA0
CLK_EN
D
Q
CLK
nCLK
PCLK
nPCLK
CLK_SEL
MR
LE
0
1
÷1
÷2
QB0
nQB0
QB1
nQB1
QA1
nQA1
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
MR
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
V
CC
QA1
nQA1
QB0
nQB0
V
CC
QB1
nQB1
ICS8737-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
8737AG-11
www.idt.com
1
REV. C AUGUST 9, 2010
L
OW
S
KEW
,
÷
1/÷2
÷
D
IFFERENTIAL
-
TO
- 3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
Name
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
Power
Power
Input
Input
Input
Input
Input
Unused
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
Pullup
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
ICS8737-11
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Pullup
No connect.
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs QXx to go low and the inver ted outputs
9
MR
Input
Pulldown
nQXx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
Power
Positive supply pins.
10, 13, 18
V
CC
11, 12
nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
14, 15
nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
16, 17
nQA1, QA1 Output
19, 2 0
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8737AG-11
www.idt.com
2
REV. C AUGUST 9, 2010
L
OW
S
KEW
,
÷
1/÷2
÷
D
IFFERENTIAL
-
TO
- 3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
CLK_EN
X
0
0
1
CLK_SEL
X
0
1
0
Selected Source
X
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
QA0, QA1
LOW
Disabled; LOW
Disabled; LOW
Enabled
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
Outputs
nQA0, nQA1
QB0, QB1
LOW
Disabled; LOW
Disabled; LOW
Enabled
nQB0, nQB1
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
ICS8737-11
0
1
1
PCLK, nPCLK
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown if Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
nCLK, nPCLK
CLK, PCLK
Disabled
Enabled
CLK_EN
nQA0, nQA1,
nQB0, nQB1
QA0, QA1,
QB0, QB1
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
QAx
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQAx
HIGH
LOW
HIGH
LOW
LOW
HIGH
QBx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQBx
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8737AG-11
www.idt.com
3
REV. C AUGUST 9, 2010
L
OW
S
KEW
,
÷
1/÷2
÷
D
IFFERENTIAL
-
TO
- 3.3V LVPECL C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS8737-11
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
CLK_EN, CLK_SEL, MR
CLK_EN, CLK_SEL, MR
Input High Current
Input Low Current
CLK_EN
CLK_SEL, MR
CLK_EN
CLK_SEL,MR
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.765
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8737AG-11
www.idt.com
4
REV. C AUGUST 9, 2010
L
OW
S
KEW
,
÷
1/÷2
÷
D
IFFERENTIAL
-
TO
- 3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
0.3
V
EE
+ 1.5
V
CC
- 1.4
V
CC
- 2.0
1
V
CC
V
CC
- 0.9
V
CC
- 1.7
1.0
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
ICS8737-11
V
SWING
Peak-to-Peak Output Voltage Swing
0.65
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(b)
t
sk(pp)
t
jit
t
R
t
F
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 4
Bank A
Bank B
CLK, nCLK
PCLK, nPCLK
IJ 650MHz
1.3
1.2
Test Conditions
Minimum
Typical
Maximum
650
1.7
1.6
60
20
35
200
0.04
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
700
700
52
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
%
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section, NOTE 5
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
48
50
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
8737AG-11
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5
REV. C AUGUST 9, 2010
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