Low Skew, 1-to-11 LVCMOS/LVTTL
Clock Multiplier/Zero Delay Buffer
G
ENERAL
D
ESCRIPTION
The ICS87952I-147 is a low voltage, low skew
LVCMOS/LVTTL Clock Generator and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance Clock
Solutions from IDT. With output frequencies up to
180MHz, the ICS87952I-147 is targeted for high
performance clock applications. Along with a fully integrated PLL,
the ICS87952I-147 contains frequency configurable outputs and
an external feedback input for regenerating clocks with “zero de-
lay”.
ICS87952I-147
DATA SHEET
F
EATURES
•
Fully integrated PLL
•
Eleven LVCMOS / LVTTL outputs, 7Ω typical output impedance
•
LVCMOS / LVTTL REF_CLK input
•
Output frequency range up to 180MHz at V
DD
= 3.3V ± 5%
•
VCO range: 240MHz - 480MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 100ps (maximum)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
For test and system debug purposes, the nPLL_EN input allows
the PLL to be bypassed. When HIGH, the MR/nOE input resets
the internal dividers and forces the outputs to the high impedance
state.
The low impedance LVCMOS/LVTTL outputs of the ICS87952I-
147 are designed to drive terminated transmission lines. The ef-
fective fanout of each output can be doubled by utilizing the abil-
ity of each output to drive two series terminated transmission lines.
B
LOCK
D
IAGRAM
nPLL_EN
P
IN
A
SSIGNMENT
GNDO
GNDO
V
DDO
V
DDO
QB1
QB0
QA4
QA3
REF_CLK
PHASE
DETECTOR
VCO
240 - 480MHz
1
0
÷2
0
÷4/÷6
1
24 23 22 21 20 19 18 17
QA0
QA1
QA2
V
DDO
QB2
QB3
GNDO
GNDO
QC0
QC1
÷4/÷2
25
26
27
28
29
30
31
32
1
VCO_SEL
16
15
14
V
DDO
QA2
QA1
GNDO
QA0
V
DD
V
DDA
nPLL_EN
FB_IN
LFP
QA3
QA4
ICS87952I-147
13
12
11
10
9
VCO_SEL
F_SELA
QB0
QB1
V
DDO
2
F_SELC
3
F_SELB
4
F_SELA
MR/nOE
5
REF_CLK
6
GNDI
7
FB_IN
8
F_SELB
QB2
QB3
÷2/÷4
QC0
QC1
F_SELC
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
ICS87952AYI-147 REVISION C AUGUST 4, 2009
1
©2009
Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet
LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
Name
VCO_SEL
F_SELC
F_SELB
F_SELA
Input
Input
Input
Input
Type
Description
Pulldown VCO select input. LVCMOS / LVTTL interface levels.
Determines output divider values for Bank C as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank B as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Active High Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are in Hi-Z.
Pulldown
When logic LOW, the internal dividers and the outputs are enabled.
Reset not required on power-up. LVCMOS / LVTTL interface levels.
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Internal power supply ground.
Feedback input to phase detector for generating clocks with
Pulldown
"zero delay". LVCMOS / LVTTL interface levels.
PLL select input. Selects between REF_CLK and the PLL.
Pulldown When HIGH, selects REF_CLK. When LOW, selects PLL.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Bank A clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output power supply ground.
Output supply pins.
Bank B clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
5
6
7
8
9
10
11
12, 14,
15, 18, 19
13, 17,
24, 28, 29
16, 20,
21, 25, 32
22, 23,
26, 27
30, 31
MR/nOE
REF_CLK
GNDI
FB_IN
nPLL_EN
V
DDA
V
DD
QA0, QA1,
QA2, QA3, QA4
GNDO
V
DDO
QB0, QB1,
QB2, QB3
QC0, QC1
Input
Input
Power
Input
Input
Power
Power
Output
Power
Power
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
V
DD
, V
DDO
= 3.465V
25
7
Maximum
Units
pF
kΩ
pF
Ω
T
ABLE
3A. F_SEL
X
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
F_SELA
0
1
Output
QA0:QA4
÷4
÷6
Input
F_SELB
0
1
Output
QB0:QB3
÷4
÷2
Input
F_SELC
0
1
Output
QC0:QC1
÷2
÷4
T
ABLE
3B. VCO_SEL C
ONTROL
S
ELECT
F
UNCTION
T
ABLE
Control Input
VCO_SEL
MR/nOE
nPLL_EN
Logic 0
fVCO
Output Enable
Enable PLL
Logic 1
fVCO/2
High-Impedance
Disable PLL
ICS87952AYI-147 REVISION C AUGUST 4, 2009
2
©2009
Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet
LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
15
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
160
20
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
REF_CLK,
Input
MR/nOE, FB_IN, VCO_SEL,
High Current
F_SELA:F_SELC, nPLL_EN
REF_CLK,
Input
MR/nOE, FB_IN, VCO_SEL,
Low Current
F_SELA:F_SELC, nPLL_EN
Output High Voltage
Output Low Voltage
Test Conditions
Minimum Typical
2
-0.3
V
DD
= V
IN
= 3.465V
Maximum
V
DD
+ 0.3
0.8
12 0
Units
V
V
µA
I
IL
V
OH
V
OL
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -20mA
I
OL
= 20mA
-120
2. 4
0.5
µA
V
V
T
ABLE
5. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
f
REF
the divider selection and the VCO lock range.
Test Conditions
Minimum
Typical
Maximum
100
Units
MHz
ICS87952AYI-147 REVISION C AUGUST 4, 2009
3
©2009
Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet
LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
f
VCO
Parameter
Maximum
Output Frequency
(PLL Mode)
QC, QB (
÷
2)
QA, QB, QC (
÷
4)
Test Conditions
Minimum
180
120
80
REF_CLK = 50MHz
-100
240
Any Frequency
200
480
150
100
100
50
Output Frequencies Mixed
Same Frequency
Input Frequency = 20MHz,
QAx = FB_IN = 20MHz,
QBx = QCx = 30MHz,
VCO_SEL = Logic 1 (÷2),
F_SELA = Logic 1 (÷6),
F_SELB = Logic 0 (÷4),
F_SELC = Logic 1 (÷4)
Output Frequencies Mixed
Same Frequency
0.8V to 2.0V
0.10
1.5
2
47
50
400
100
Typical
Maximum
Units
MHz
MHz
MHz
ps
MHz
ps
ps
ps
ps
ps
ps
QA (
÷
6)
Propagation Delay, REF_CLK to FB_IN
Delay, (Static Phase Offset); NOTE 1
PLL VCO Lock Range
All Outputs
Output Skew;
NOTE 2, 3
Within QA Bank
Within QB Bank
Within QC Bank
t
sk(o)
t
jit(cc)
Cycle-to-Cycle Jitter;
NOTE 3
All Outputs
250
ps
t
jit(per)
t
L
t
R
/ t
F
t
PLZ
, t
PHZ
t
PZL
odc
Period Jitter
PLL Lock Time
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Output Duty Cycle
All Outputs
450
100
10
1.0
8
10
53
ps
ps
ms
ns
ns
ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditons.
NOTE: All parameters measured at f
MAX
unless noted otherwise.
NOTE: All outputs loaded at 50
Ω
to V
DDO
/2.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ICS87952AYI-147 REVISION C AUGUST 4, 2009
4
©2009
Integrated Device Technology, Inc.
ICS87952I-147 Data Sheet
LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
V
DD
,
V
DDO
SCOPE
Qx
V
DDO
2
LVCMOS
GND
Qx
V
DDO
Qy
2
tsk(o)
-1.65V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
V
OH
QAx,
QBx,
QCx
V
DDO
V
DDO
V
V
REF
2
DDO
2
tcycle
n
2
➤
tcycle
n+1
➤
tjit(cc)
=
tcycle
n –
tcycle
n+1
1000 Cycles
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
V
OL
C
YCLE
-
TO
-C
YCLE
J
ITTER
REF_CLK
V
DD
2
FB_IN
t
PD
V
DDO
2
REF_CLK
TO
FB_IN D
ELAY
V
DDO
QAx,
QBx,
QCx
2
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
ICS87952AYI-147 REVISION C AUGUST 4, 2009
5
©2009
Integrated Device Technology, Inc.
➤
➤
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
P
ERIOD
J
ITTER
2V
QAx,
QBx,
QCx
2V
0.8V
0.8V
t
R
t
F
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DDO
2
V
DDO
2
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
