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IS61VPS102436B-250TQLI

产品描述sram 36m, 2.5V, 250mhz sync sram
产品类别半导体    其他集成电路(IC)   
文件大小1MB,共35页
制造商All Sensors
标准  
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IS61VPS102436B-250TQLI概述

sram 36m, 2.5V, 250mhz sync sram

IS61VPS102436B-250TQLI规格参数

参数名称属性值
ManufactureISSI
产品种类
Product Category
SRAM
RoHSYes
系列
Packaging
Tray
工厂包装数量
Factory Pack Quantity
72

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IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
1M x 36, 1M x 32, 2M x 18
36 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for BGA package
• Power Supply
LPS: V
dd
3.3V (+ 5%),
V
ddq
3.3V/2.5V (+ 5%)
VPS: V
dd
2.5V (+ 5%),
V
ddq
2.5V (+ 5%)
VVPS: V
dd
1.8V (+ 5%),
V
ddq
1.8V (+ 5%)
• JEDEC 100-Pin QFP, 119-ball BGA, and 165-
ball BGA packages
• Lead-free available
AUgUST 2014
DESCRIPTION
The 36Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and net-
working applications. The IS61LPS/VPS102436B and
IS64LPS102436B are organized as 1,048,476 words by
36 bits. The IS61LPS102432B is organized as 1,048,476
words by 32 bits. The IS61LPS/VPS204818B is organized
as 2,096,952 words by 18 bits. Fabricated with
ISSI
's
advanced CMOS technology, the device integrates a
2-bit burst counter, high-speed SRAM core, and high-
drive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
250
2.8
4
250
200
3.1
5
200
166
3.8
6
166
Units
ns
ns
MHz
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
8/5/2014
1

IS61VPS102436B-250TQLI相似产品对比

IS61VPS102436B-250TQLI IS61VPS102436B-250TQLI-TR IS61VPS102436B-250B3L-TR IS61VVPS204818B-166B3LI-TR IS61LPS102436B-200TQLI-TR IS61VVPS204818B-166B3LI IS61LPS204818B-200B3L-TR IS61LPS102436B-200TQLI IS61LPS204818B-200B3L IS61VPS102436B-250B3L
描述 sram 36m, 2.5V, 250mhz sync sram sram 36m, 2.5V, 250mhz sync sram sram 36mb 2.5v 250mhz 1M x 36 sync sram sram 36mb 2.5V 166mhz 2M x 18 sync sram sram 36mb 200mhz 3.3V or 2.5V 1mx36 sync sram sram 36mb 2.5V 166mhz 2M x 18 sync sram sram 36mb 200mhz 3.3V or 2.5V 1mx36 sync sram sram 36mb 200mhz 3.3V or 2.5V 1mx36 sync sram sram 36mb 200mhz 3.3V or 2.5V 1mx36 sync sram sram 36mb 2.5v 250mhz 1M x 36 sync sram
Manufacture ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI
产品种类
Product Category
SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
RoHS Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Memory Size - - 36 Mbi 36 Mbi 36 Mbi 36 Mbi 36 Mbi 36 Mbi 36 Mbi 36 Mbi
Organizati - - 1 M x 36 2 M x 18 1 M x 36 2 M x 18 2 M x 18 1 M x 36 2 M x 18 1 M x 36
Access Time - - 2.6 ns 3.5 ns 3.1 ns 3.5 ns 3.1 ns 3.1 ns 3.1 ns 2.6 ns
电源电压-最大
Supply Voltage - Max
- - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Supply Voltage - Mi - - 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
Maximum Operating Curre - - 360 mA 340 mA 360 mA 340 mA 340 mA 360 mA 340 mA 360 mA
最大工作温度
Maximum Operating Temperature
- - + 70 C + 85 C + 85 C + 85 C + 70 C + 85 C + 70 C + 70 C
最小工作温度
Minimum Operating Temperature
- - 0 C - 40 C - 40 C - 40 C 0 C - 40 C 0 C 0 C
安装风格
Mounting Style
- - SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
封装 / 箱体
Package / Case
- - PBGA-165 PBGA-165 TQFP-100 PBGA-165 PBGA-165 TQFP-100 PBGA-165 PBGA-165
Maximum Clock Frequency - - 250 MHz 166 MHz 200 MHz 166 MHz 200 MHz 200 MHz 200 MHz 250 MHz
Memory Type - - Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous
类型
Type
- - Pipelined SRAM Pipelined SRAM Pipelined SRAM Pipelined SRAM Pipelined SRAM Pipelined SRAM Pipelined SRAM Pipelined SRAM

 
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