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IS61LF204836B-7.5TQLI-TR: 产品描述sram 72m 3.3V/2.5V, 7.5ns 2mx36 sync sram; 产品类别半导体其他集成电路（IC）; 文件大小1MB，共34页; 制造商All Sensors; 标准

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IS61LF204836B-7.5TQLI-TR概述

sram 72m 3.3V/2.5V, 7.5ns 2mx36 sync sram

IS61LF204836B-7.5TQLI-TR规格参数

参数名称	属性值
Manufacture	ISSI
产品种类 Product Category	SRAM
RoHS	Yes
Memory Size	72 Mbi
Organizati	2 M x 36
Access Time	7.5 ns
电源电压-最大 Supply Voltage - Max	3.3 V
Supply Voltage - Mi	2.5 V
Maximum Operating Curre	240 mA
最大工作温度 Maximum Operating Temperature	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	TQFP-100
系列 Packaging	Reel
Maximum Clock Frequency	117 MHz
Memory Type	Synchronous
工厂包装数量 Factory Pack Quantity	800
类型 Type	Synchronous Flow-Through SRAM

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IS61LF204836B, IS61VF/VVF204836B

IS61LF409618B, IS61VF/VVF409618B

2M x 36, 4M x 18

72 Mb SYNCHRONOUS

FLOW-THROUGH

STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LF: V

3.3V (+ 5%),

ddq

3.3V/2.5V (+ 5%)

VF: V

2.5V (+ 5%),

ddq

2.5V (+ 5%)

VVF: V

1.8V (+ 5%),

ddq

1.8V (+ 5%)

• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-

pin PBGA packages

• Lead-free available

ADVANCED INFORMATION

OCTOBER 2012

DESCRIPTION

The 72Mb product family features high-speed, low-power

synchronous static

RAMs

designed to provide burstable,

high-performance memory for communication and network-

ing applications. The

IS61LF/VF204836B is organized as

2,096,952 words by 36 bits. The IS61LF/VF409618B

organized as 4,193,904 words by 18 bits. Fabricated with

ISSI

's advanced CMOS technology, the device integrates

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be writ-

ten. Byte write operation is performed by using byte write

enable (BWE)

input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00B

10/15/2012

IS61LF204836B-7.5TQLI-TR相似产品对比

	IS61LF204836B-7.5TQLI-TR	IS61LF204836B-7.5TQLI
描述	sram 72m 3.3V/2.5V, 7.5ns 2mx36 sync sram	sram 72m 3.3V/2.5V, 7.5ns 2mx36 sync sram
Manufacture	ISSI	ISSI
产品种类 Product Category	SRAM	SRAM
RoHS	Yes	Yes
Memory Size	72 Mbi	72 Mbi
Organizati	2 M x 36	2 M x 36
Access Time	7.5 ns	7.5 ns
电源电压-最大 Supply Voltage - Max	3.3 V	3.3 V
Supply Voltage - Mi	2.5 V	2.5 V
Maximum Operating Curre	240 mA	240 mA
最大工作温度 Maximum Operating Temperature	+ 85 C	+ 85 C
最小工作温度 Minimum Operating Temperature	- 40 C	- 40 C
安装风格 Mounting Style	SMD/SMT	SMD/SMT
封装 / 箱体 Package / Case	TQFP-100	TQFP-100
系列 Packaging	Reel	Tray
Maximum Clock Frequency	117 MHz	117 MHz
Memory Type	Synchronous	Synchronous
工厂包装数量 Factory Pack Quantity	800	72
类型 Type	Synchronous Flow-Through SRAM	Synchronous Flow-Through SRAM

IS61LF204836B-7.5TQLI-TR

IS61LF204836B-7.5TQLI-TR概述

IS61LF204836B-7.5TQLI-TR规格参数

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