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IS61LF102418A-6.5TQL

产品描述sram 18m (1mx18) 6.5ns sync sram 3.3v
产品类别半导体    其他集成电路(IC)   
文件大小299KB,共36页
制造商All Sensors
标准  
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IS61LF102418A-6.5TQL概述

sram 18m (1mx18) 6.5ns sync sram 3.3v

IS61LF102418A-6.5TQL规格参数

参数名称属性值
ManufactureISSI
产品种类
Product Category
SRAM
RoHSYes
Memory Size18 Mbi
Access Time6.5 ns
电源电压-最大
Supply Voltage - Max
3.465 V
Supply Voltage - Mi3.135 V
Maximum Operating Curre250 mA
最大工作温度
Maximum Operating Temperature
+ 70 C
最小工作温度
Minimum Operating Temperature
0 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TQFP-100
系列
Packaging
Tray
Maximum Clock Frequency133 MHz
工厂包装数量
Factory Pack Quantity
72
类型
Type
Synchronous

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IS61LF25672A IS61VF25672A
IS61LF51236A IS61VF51236A
IS61LF102418A IS61VF102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LF: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VF: V
DD
2.5V + 5%, V
DDQ
2.5V + 5%
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball
PBGA and 165-pin PBGA packages.
• Lead-free available
JULY 2010
DESCRIPTION
The
ISSI
IS61LF/VF25672A, IS61LF/VF51236A and
IS61LF/VF102418A are high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LF/VF25672A is organized as
262,144 words by 72 bits. The IS61LF/VF51236A is orga-
nized as 524,288 words by 36 bits. The IS61LF/VF102418A
is organized as 1,048,576 words by 18 bits. Fabricated
with
ISSI
's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic cir-
cuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. K
07/29/2010
1

IS61LF102418A-6.5TQL相似产品对比

IS61LF102418A-6.5TQL IS61VF51236A-7.5TQLI IS61LF51236A-6.5B2LI-TR IS61VF51236A-7.5TQLI-TR IS61LF102418A-6.5TQL-TR IS61LF102418A-7.5TQLI-TR IS61LF51236A-7.5TQLI-TR IS61LF51236A-6.5B2LI
描述 sram 18m (1mx18) 6.5ns sync sram 3.3v sram 18m (512kx36) 7.5ns sync sram 2.5v sram 18m (512kx36) 6.5ns sync sram 3.3v sram 18m (512kx36) 7.5ns sync sram 2.5v sram 18m (1mx18) 6.5ns sync sram 3.3v sram 18m (1mx18) 7.5ns sync sram 3.3v sram 18mb 512kx36 7.5ns sync sram 3.3v sram 18m (512kx36) 6.5ns sync sram 3.3v
Manufacture ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI
产品种类
Product Category
SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
RoHS Yes Yes Yes Yes Yes Yes Yes Yes
Memory Size 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi 18 Mbi
Access Time 6.5 ns 7.5 ns 6.5 ns 7.5 ns 6.5 ns 7.5 ns 7.5 ns 6.5 ns
电源电压-最大
Supply Voltage - Max
3.465 V 2.625 V 3.465 V 2.625 V 3.465 V 3.465 V 3.465 V 3.465 V
Supply Voltage - Mi 3.135 V 2.375 V 3.135 V 2.375 V 3.135 V 3.135 V 3.135 V 3.135 V
Maximum Operating Curre 250 mA 250 mA 275 mA 250 mA 250 mA 250 mA 250 mA 275 mA
最大工作温度
Maximum Operating Temperature
+ 70 C + 85 C + 85 C + 85 C + 70 C + 85 C + 85 C + 85 C
最小工作温度
Minimum Operating Temperature
0 C - 40 C - 40 C - 40 C 0 C - 40 C - 40 C - 40 C
安装风格
Mounting Style
SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
封装 / 箱体
Package / Case
TQFP-100 TQFP-100 BGA TQFP-100 TQFP-100 TQFP-100 TQFP-100 BGA
系列
Packaging
Tray Tray Reel Reel Reel Reel Reel Tray
Maximum Clock Frequency 133 MHz 117 MHz 133 MHz 117 MHz 133 MHz 117 MHz 117 MHz 133 MHz
工厂包装数量
Factory Pack Quantity
72 72 1000 800 800 800 800 84
类型
Type
Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous

 
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