liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
8/6/2014
1
IS43/46LD16640A
IS43/46LD32320A
BALL AssiGnMents And descRiptions
134-ball FBGA (x32), 0.65mm pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DNU
DNU
VDD1
VSS
VSSCA
VDDCA
VDD2
VDDCA
VSSCA
CKE
CS_n
CA4
VSSCA
VSS
VDD1
DNU
DNU
2
DNU
NC
VSS
VDD2
CA9
CA6
CA5
VSS
NC
RFU
RFU
CA3
VDDCA
VDD2
VSS
NC
DNU
3
NC
RFU
ZQ
CA8
CA7
Vref(CA)
CK_c
CK_t
RFU
RFU
CA2
CA1
CA0
NC
NC
4
5
VDD2
VSS
VDDQ
DQ28
VSSQ
DQS1_c
DM1
VSSQ
DM0
DQS0_c
VSSQ
DQ19
VDDQ
VSS
VDD2
6
VDD1
VSSQ
DQ30
DQ24
DQ11
DQS1_t
VDDQ
VDDQ
VDDQ
DQS0_t
DQ4
DQ23
DQ17
VSSQ
VDD1
7
DQ31
VDDQ
DQ27
DM3
DQ13
DQ10
VDD2
DQ5
DQ2
DM2
DQ20
VDDQ
DQ16
8
DQ29
DQ25
DQS3_t
DQ15
DQ14
DQ9
VSS
DQ6
DQ1
DQ0
DQS2_t
DQ22
DQ18
9
DNU
DQ26
VSSQ
DQS3_c
VDDQ
DQ12
DQ8
Vref(DQ)
DQ7
DQ3
VDDQ
DQS2_c
VSSQ
DQ21
DNU
10
DNU
DNU
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
DNU
DNU
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQ
CA
Power
Ground
No ball
ZQ
Clock
NC, DNU, RFU
1
2
3
4
5
6
7
8
9
10
Top View (ball down)
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
8/6/2014
IS43/46LD16640A
IS43/46LD32320A
BALL AssiGnMents And descRiptions
134-ball FBGA (x16), 0.65mm pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DNU
DNU
VDD1
VSS
VSSCA
VDDCA
VDD2
VDDCA
VSSCA
CKE
CS_n
CA4
VSSCA
VSS
VDD1
DNU
DNU
2
DNU
NC
VSS
VDD2
CA9
CA6
CA5
VSS
NC
RFU
RFU
CA3
VDDCA
VDD2
VSS
NC
DNU
3
NC
RFU
ZQ
CA8
CA7
Vref(CA)
CK_c
CK_t
RFU
RFU
CA2
CA1
CA0
NC
NC
4
5
VDD2
VSS
VDDQ
NC
VSSQ
DQS1_c
DM1
VSSQ
DM0
DQS0_c
VSSQ
NC
VDDQ
VSS
VDD2
6
VDD1
VSSQ
NC
NC
DQ11
DQS1_t
VDDQ
VDDQ
VDDQ
DQS0_t
DQ4
NC
NC
VSSQ
VDD1
7
NC
VDDQ
NC
NC
DQ13
DQ10
VDD2
DQ5
DQ2
NC
NC
VDDQ
NC
8
NC
NC
NC
DQ15
DQ14
DQ9
VSS
DQ6
DQ1
DQ0
NC
NC
NC
9
DNU
NC
VSSQ
NC
VDDQ
DQ12
DQ8
Vref(DQ)
DQ7
DQ3
VDDQ
NC
VSSQ
NC
DNU
10
DNU
DNU
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
DNU
DNU
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQ
CA
Power
Ground
No ball
ZQ
Clock
NC, DNU, RFU
1
2
3
4
5
6
7
8
9
10
Top View (ball down)
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
8/6/2014
3
IS43/46LD16640A
IS43/46LD32320A
168-ball FBGA - 12mm x 12mm (x32), 0.5mm pitch
1
2
DNU
DNU
V
DD2
NC
NC
V
SS
1
NC
NC
V
SS
1
NC
NC
V
SS
V
DD1
V
REFCA
V
DD2
CA8
V
DDCA
CA6
V
DDCA
CK
V
DD2
DNU
DNU
2
CS#
CKE
3
NC
NC
4
V
DD1
V
SS
5
CA1
CA0
6
V
SSCA
CA3
CA4
V
SS
9
1
V
DD2
NC
10
V
SS
NC
11
DQ16
V
DDQ
DQ18
DQ20
V
DDQ
DQ22 DQS2
V
SSQ
DQ21 DQ23
15
16
17
V
DDQ
DM2
3
NC
V
DD1
4
NC
NC
5
NC
V
SS
1
6
NC
NC
7
NC
NC
8
NC
V
SS
1
9
NC
NC
10
NC
V
SS
11
V
DD1
V
DD2
12
V
SSQ
13
14
15
16
17
18
19
20
21
V
SS
22
DNU
23
DNU
DNU
V
SSQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
DNU
DNU
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ZQ
V
SS
CA9
CA7
V
SSCA
CA5
CK#
V
SS
DNU
DNU
1
DQ30 DQ29
DQ28
V
SSQ
DQ26 DQ25
V
SSQ
DQS#3
V
DD1
V
DDQ
DM3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
DQ31
V
DDQ
DQ27
V
DDQ
DQ24 DQS3
V
DD2
DNU
DQ15
V
DDQ
DQ14
DQ12 DQ13
DQ11
V
SSQ
V
DDQ
DQ10
DQ8
DQS1
DQ9
V
SSQ
V
DDQ
DQS#1
V
DD2
V
REFDQ
V
DD1
DM1
V
SS
DM0
DQS#0 V
SSQ
V
DDQ
DQS0
DQ6
DQ5
V
DDQ
DQ2
DQ1
V
DDQ
V
DD2
DNU
V
SS
21
DNU
22
DQ7
V
SSQ
DQ4
DQ3
V
SSQ
DQ0
DNU
DNU
23
CA2
V
DDCA
7
8
V
SSQ
DQ17 DQ19
12
13
14
V
SSQ
DQS#2
V
DD1
18
19
20
Top View (ball down)
Note:
1. Balls labeled Vss
1
(at coordinates B5, B8, F2, J2, AC9) may be connected to Vss or left unconnected.
2. Balls indicated as (NC) are no connects.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
8/6/2014
IS43/46LD16640A
IS43/46LD32320A
inpUt/oUtpUt FUnctionAL descRiption
pad definition and description
Name
CK_t, CK_c
Type
Input
Description
Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA
inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR)
inputs, CS_n and CKE, are sampled at the positive Clock edge.
Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is
defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is
defined by the crosspoint of a falling CK_t and a rising CK_c.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
therefore device input buffers and output drivers. Power savings modes are entered and
exited through CKE transitions.
CKE is considered part of the command code. See
Command Truth Table
for command
code descriptions.
CKE is sampled at the positive Clock edge.
Chip Select: CS_n is considered part of the command code. See
Command Truth Table
for command code descriptions.
CS_n is sampled at the positive Clock edge.
DDR Command/Address Inputs: Uni-directional command/address bus inputs.
CA is considered part of the command code. See
Command Truth Table
for command
code descriptions.
Data Inputs/Output: Bi-directional data bus
CKE
Input
CS_n
Input
CA0 - CA9
Input
DQ0 - DQ15
(x16)
DQ0 - DQ31
(x32)
I/O
I/O
DQS0_t,
DQS0_c,
DQS1_t,
DQS1_c
(x16)
DQS0_t -
DQS3_t,
DQS0_c -
DQS3_c
(x32)
Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for
read and write data) and differential (DQS_t and DQS_c). It is output with read data and
input with write data. DQS_t is edge-aligned to read data and centered with write data.
For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and
DQS1_c to the data on DQ8 - DQ15.
For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and
DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23,
DQS3_t and DQS3_c to the data on DQ24 - DQ31.
Input
DM0-DM1
(x16)
DM0 - DM3
(x32)
Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the
input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of
DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or
DQS_c).
DM0 is the input data mask signal for the data on DQ0-7.
For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is
the input data mask signal for the data on DQ24-31.
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