CTSLV353
Low Phase Noise LVPECL Buffer and Translator
QFN8, SON8
FEATURES
LVPECL Outputs Optimized for Very Low
Phase Noise (-165dBc/Hz)
Up to 800MHz Bandwidth
Selectable ÷1, ÷2 Output
Selectable Enable Logic
3.0V to 3.6V Operation
RoHS Compliant Pb Free Packages
BLOCK DIAGRAM
DESCRIPTION
The CTSLV353 is a sine wave/CMOS to LVPECL buffer/translator optimized for very low phase noise (-
165dBc/Hz). It is particularly useful in converting crystal or SAW based oscillators into LVPECL outputs for up
800MHz of bandwidth. For greater bandwidth, refer to the
CTSLV363.
The CTSLV353 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2
modes as well as active high enable or active low enable to oscillator designers. Refer to Table 1 for the
comparison of parts within the CTSLV35x and CTSLV363 family.
ENGINEERING NOTES
Functionality
Table 1 details the differences between the family parts to assist designers in selecting the optimal part for
their design.
Table 2 lists the specific CTSLV353 functional operation.
Figure 1 plots the S-parameters of the D input.
Table 1
Part Number
CTSLV351
CTSLV353
CTSLV363
Divide Ratio
÷1
Selectable ÷1 or ÷2
Selectable ÷1 or ÷2
EN Logic
active HIGH
selectable
selectable
EN Pull-Up /
Pull-Down
Pull-up
selectable
selectable
Bandwidth
> 800MHz
> 800MHz
≥
1GHz
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
1
Rev B0215
CTSLV353
Low Phase Noise LVPECL Buffer and Translator
QFN8, SON8
Table 2 - CTSLV353 Functional Operation, ÷1 mode
Inputs
EN
Low, NC
High
Low
High, NC
Low
DIV_SEL
Low, NC
High
Outputs
`Q
High
Low
Z
High
Low
Z
Divide Ratio
÷1
÷2
Part Number
EN_SEL
High, NC
D
Low
High
X
Low
High
X
Q
Low
High
Z
Low
High
Z
CTSLV353
Figure 1 - S11, Parameters, D Input
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
2
Rev B0215
CTSLV353
Low Phase Noise LVPECL Buffer and Translator
QFN8, SON8
Input Termination
The D input bias is V
DD
/2 fed through an internal 10k resistor. For clock applications, an input signal of at
least 750mV
PP
ensures the CTSLV353 meets AC specifications. The input should also be AC coupled to
maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and V
DD
without
damage or waveform degradation.
Figure 2 - Input Termination
Output Termination Techniques
The LVPECL compatible output stage of the CTSLV353 uses a current drive topology to maximize switching
speed as illustrated below in Figure 3. Two current source PMOS transistors (M1-M2) feed the output pins.
M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2.
This produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through
the output pin. The associated output voltage swings match LVPECL levels when external 50 resistors
terminate the outputs.
Both Q and Q should always be terminated identically to avoid waveform distortion and circulating current
¯
caused by unsymmetrical loads. This rule should be followed even if only one output is in use.
V
DD
(+3.3 V)
Output
Stage
V
bp
M1
M2
External
Circuitry
21.1mA
Q
Q
21.1mA
D
M3
M4
21.1mA - High
5.1mA - Low
50Ω
50Ω
V
bn
M5
16mA
V
TT
= V
DD
- 2.0V
Figure 3 - Typical Output Termination
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
3
Rev B0215
CTSLV353
Low Phase Noise LVPECL Buffer and Translator
QFN8, SON8
Dual Supply LVPECL Output Termination
The standard LVPECL loads are a pair of 50 resistors connected between the outputs and V
DD
-2.0V (Figure
3). The resistors provide both the DC and the AC loads, assuming 50 interconnect. If an additional supply is
available within the application, a four resistor termination configuration is possible (Figure 4).
Figure 4 - Dual Supply Output Termination
Three Resistor Termination
Another termination variant eliminates the need for the additional supply (Figure 5). Alternately three resistors
and one capacitor accomplish the same termination and reduce power consumption.
Figure 5 - Three Resistor Termination
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
4
Rev B0215
CTSLV353
Low Phase Noise LVPECL Buffer and Translator
QFN8, SON8
Evaluation Board (EBP53)
CTS’s evaluation board, EBP53, provides the most convenient way to test and prototype CTSLV353 series
circuits. Built for the CTSLV353QG 1.5x1.0mm package, it is designed to support both dual and single supply
operation. Dual supply operation (V
DD
=+2.0V, V
SS
=-1.3V) enables direct coupling to 50 time domain test
equipment (Figure 6).
Figure 6 - Split Supply LVPECL Output Termination
AC Termination
Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 7
below shows the AC coupling technique. The 200 resistors form the required DC loads, and the 50
resistors provide the AC termination. The parallel combination of the 200 and 50 resistors results in a net
40 AC load termination. In many cases this will work well. If necessary, the 50 resistors can be increased
to about 56. Alternately, bias tees combined with current setting resistors will eliminate the lowered AC load
impedance. The 50 resistors are typically connected to ground but can be connected to the bias level
needed by the succeeding stage.
Figure 7 - AC Termination
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
5
Rev B0215
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