P89LPC9151/9161/9171
8-bit microcontroller with accelerated two-clock 80C51 core,
2 kB 3 V byte-erasable flash with 8-bit ADC
Rev. 02 — 9 February 2010
Product data sheet
1. General description
The P89LPC9151/9161/9171 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the device in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
2 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
256-byte RAM data memory.
4-input multiplexed 8-bit ADC/single DAC output. Two analog comparators with
selectable inputs and reference source.
Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC9171) may be configured to
toggle a port output upon timer overflow or to become a PWM output.
A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
2
C-bus
communication port.
SPI communication port (P89LPC9161).
2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
16-pin TSSOP with 12 I/O pins minimum and up to 14 I/O pins while using on-chip
oscillator and reset options (P89LPC9161/9171), and 14-pin TSSOP packages with 10
I/O pins minimum and up to 12 I/O pins while using on-chip oscillator and reset options
(P89LPC9151).
NXP Semiconductors
P89LPC9151/9161/9171
8-bit microcontroller with 8-bit ADC
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
In-Application Programming (IAP-Lite) and byte erase allows code memory to be used
for non-volatile data storage.
Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to
±5
%,
requiring no external components. The watchdog prescaler is selectable from
eight values.
High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable.
Clock switching on the fly among internal RC oscillator, watchdog oscillator, external
clock input provides optimal support of minimal power active mode with fast switching
to maximum performance.
Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
μA
(total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A software reset function is also available.
Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
High current sourcing/sinking (20 mA) at 4 I/O pins on the P89LPC9151, 3 I/O pins on
the P89LPC9161 and 5 I/O pins on the P89LPC9171. All other port pins have high
sinking capability (20 mA). A maximum limit is specified for the entire chip.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
Only power and ground connections are required to operate the
P89LPC9151/9161/9171 when internal reset option is selected.
Four interrupt priority levels.
Five/six keypad interrupt inputs, plus two additional external interrupt inputs.
Schmitt trigger port inputs.
Second data pointer.
Emulation support.
P89LPC9151_61_71_2
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 February 2010
2 of 91
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
