FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
April 2013
FAN3226 / FAN3227 / FAN3228 / FAN3229
Dual 2-A High-Speed, Low-Side Gate Drivers
Features
Industry-Standard Pinouts
4.5-V to 18-V Operating Range
3-A Peak Sink/Source at V
DD
= 12 V
2.4 A-Sink / 1.6-A Source at V
OUT
= 6 V
Choice of TTL or CMOS Input Thresholds
Four Versions of Dual Independent Drivers:
Description
The FAN3226-29 family of dual 2 A gate drivers is
designed to drive N-channel enhancement-mode
MOSFETs in low-side switching applications by
providing high peak current pulses during the short
switching intervals. The driver is available with either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output low until the supply voltage is within the
operating range. In addition, the drivers feature matched
internal propagation delays between A and B channels
for applications requiring dual gate drives with critical
timing, such as synchronous rectifiers. This enables
connecting two drivers in parallel to effectively double
the current capability driving a single MOSFET.
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing rail-
to-rail voltage swing and reverse current capability.
The FAN3226 offers two inverting drivers and the
FAN3227 offers two non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3228 and FAN3229, each
channel has dual inputs of opposite polarity, which
allows configuration as non-inverting or inverting with an
optional enable function using the second input. If one
or both inputs are left unconnected, internal resistors
bias the inputs such that the output is pulled low to hold
the power MOSFET off.
-
-
-
Dual Inverting + Enable (FAN3226)
Dual Non-Inverting + Enable (FAN3227)
Dual Inputs in Two Pin-Out Configurations:
o
o
Compatible with FAN3225x (FAN3228)
Compatible with TPS2814D (FAN3229)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
12-ns / 9-ns Typical Rise/Fall Times (1-nF Load)
Under 20-ns Typical Propagation Delay Matched
within 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Servers
Automotive-Qualified Systems (F085 version)
Related Resources
AN-6069: Application Review and Comparative
Evaluation of Low-Side Gate Drivers
FAN3226
FAN3227
FAN3228
FAN3229
Figure 1. Pin Configurations
© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0
www.fairchildsemi.com
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
Ordering Information
Part Number
FAN3226CMPX
FAN3226CMX
FAN3226CMX_F085
FAN3226TMPX
FAN3226TMX
FAN3226TMX_F085
FAN3227CMPX
FAN3227CMX
FAN3227CMX_F085
FAN3227TMPX
FAN3227TMX
FAN3227TMX_F085
(1)
(1)
(1)
(1)
(1)
Logic
Input
Threshold
CMOS
Package
3x3 mm MLP-8
SOIC-8
SOIC-8
3x3 mm MLP-8
Packing
Method
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Quantity
per Reel
3,000
2,500
2,500
3,000
2,500
2,500
3,000
2,500
2,500
3,000
2,500
2,500
2,500
2,500
3,000
2,500
2,500
3,000
2,500
2,500
Dual Inverting Channels + Dual
Enable
TTL
SOIC-8
SOIC-8
3x3 mm MLP-8
CMOS
Dual Non-Inverting Channels +
Dual Enable
TTL
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 1
CMOS
TTL
CMOS
(1)
SOIC-8
SOIC-8
3x3 mm MLP-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
3x3 mm MLP-8
SOIC-8
SOIC-8
3x3 mm MLP-8
FAN3228CMX_F085
FAN3228TMX_F085
FAN3229CMPX
FAN3229CMX
FAN3229CMX_F085
FAN3229TMPX
FAN3229TMX
FAN3229TMX_F085
(1)
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 2
TTL
SOIC-8
SOIC-8
(1)
All standard Fairchild Semiconductor products are RoHS compliant and many are also “Green” or going green. Green means
the products are RoHS compliant AND they have limits on additional substances of Chlorine, Bromine and Antimony.
For additional
information on Fairchild’s “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
Note:
1. Qualified to AEC-Q100
© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0
www.fairchildsemi.com
2
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
Package Outlines
Figure 2. 3x3 mm MLP-8 (Top View)
Figure 3. SOIC-8 (Top View)
Thermal Characteristics
(2)
Package
8-Lead 3x3 mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Θ
JL(3)
1.6
40
Θ
JT(4)
68
31
Θ
JA(5)
43
89
Ψ
JB(6)
3.5
43
Ψ
JT(7)
0.8
3.0
Unit
°C/W
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3.
Theta_JL (
Θ
JL
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
4.
5.
6.
thermal pad) that are typically soldered to a PCB.
Theta_JT (
Θ
JT
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
7.
Theta_JA (Θ
JA
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (
Ψ
JB
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 5. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (
Ψ
JT
): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 5.
© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0
www.fairchildsemi.com
3
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226
FAN3227
FAN3228
FAN3229
Figure 4. Pin Configurations (Repeated)
Pin Definitions
Name
ENA
ENB
GND
INA
INA+
INA-
INB
INB+
INB-
OUTA
OUTB
OUTA
OUTB
Pin Description
Enable Input for Channel A.
Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
Enable Input for Channel B.
Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
Ground.
Common ground reference for input and output circuits.
Input to Channel A.
Non-Inverting Input to Channel A.
Connect to VDD to enable output.
Inverting Input to Channel A.
Connect to GND to enable output.
Input to Channel B.
Non-Inverting Input to Channel B.
Connect to VDD to enable output.
Inverting Input to Channel B.
Connect to GND to enable output.
Gate Drive Output A:
Held LOW unless required input(s) are present and V
DD
is above UVLO threshold.
Gate Drive Output B:
Held LOW unless required input(s) are present and V
DD
is above UVLO threshold.
Gate Drive Output A
(inverted from the input): Held LOW unless required input is present and V
DD
is
above UVLO threshold.
Gate Drive Output B
(inverted from the input): Held LOW unless required input is present and V
DD
is
above UVLO threshold.
Thermal Pad
(MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
Supply Voltage.
Provides power to the IC.
P1
VDD
Output Logic
FAN3226 (x=A or B)
ENx
0
0
1
(8)
FAN3227 (x=A or B)
OUTx
FAN3228 and FAN3229
(x=A or B)
INx+
0
(8)
0
(8)
INx
0
1
(8)
ENx
0
0
1
(8)
INx
0
(8)
1
0
(8)
OUTx
0
0
0
1
INx−
0
1
(8)
OUTx
0
0
1
0
0
0
1
0
0
1
(8)
1
1
0
1
(8)
1
(8)
1
(8)
1
Note:
8. Default input signal if no external connection is made.
© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0
www.fairchildsemi.com
4
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
Block Diagrams
V
DD
100k
V
DD
100k
ENA
1
V
DD
100k
8
ENB
INA
2
7
100k
OUTA
GND
3
UVLO
6
VDD
V
DD
100k
V
DD_OK
INB
4
100k
5
OUTB
Figure 5. FAN3226 Block Diagram
Figure 6. FAN3227 Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0
www.fairchildsemi.com
5
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