are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
July 2012
Subscribe
1–2
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Design Security Feature
Cyclone III LS devices offer the following design security features:
■
Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
Routing architecture optimized for design separation flow with the Quartus
®
II
software
■
■
Design separation flow achieves both physical and functional isolation
between design partitions
■
■
Ability to disable external JTAG port
Error Detection (ED) Cycle Indicator to core
■
■
Provides a pass or fail indicator at every ED cycle
Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
■
Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
Internal oscillator enables system monitor and health check capabilities
■
Increased System Integration
■
■
High memory-to-logic and multiplier-to-logic ratio
High I/O count, low-and mid-range density devices for user I/O constrained
applications
■
■
Adjustable I/O slew rates to improve signal integrity
Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
■
■
Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
■
■
■
Five outputs per PLL
Cascadable to save I/Os, ease PCB routing, and reduce jitter
Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
■
■
Remote system upgrade without the aid of an external controller
Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
Nios
®
II embedded processor for Cyclone III device family, offering low cost and
custom-fit embedded processing solutions
■
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
1–3
■
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
■
■
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 1–1
lists Cyclone III device family features.
Table 1–1. Cyclone III Device Family Features
Family
Device
EP3C5
EP3C10
EP3C16
Cyclone III
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
EP3CLS70
Cyclone III
LS
EP3CLS100
EP3CLS150
EP3CLS200
Logic
Elements
5,136
10,320
15,408
24,624
39,600
55,856
81,264
119,088
70,208
100,448
150,848
198,464
Number of
M9K
Blocks
46
46
56
66
126
260
305
432
333
483
666
891
Total RAM
Bits
423,936
423,936
516,096
608,256
1,161,216
2,396,160
2,810,880
3,981,312
3,068,928
4,451,328
6,137,856
8,211,456
18 x 18
Multipliers
23
23
56
66
126
156
244
288
200
276
320
396
PLLs
2
2
4
4
4
4
4
4
4
4
4
4
Global
Clock
Networks
10
10
20
20
20
20
20
20
20
20
20
20
Maximum
User I/Os
182
182
346
215
535
377
429
531
429
429
429
429
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
1–4
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Table 1–2
lists Cyclone III device family package options, I/O pins, and differential
channel counts.
Table 1–2. Cyclone III Device Family Package Options, I/O pin and Differential Channel Counts
Family
Package
EP3C5
EP3C10
EP3C16
Cyclone III
(8)
(1), (2), (3), (4), (5)
E144
(7)
M164
106, 28
106, 28
92, 23
—
—
—
—
—
—
—
—
—
P240
—
—
F256
182, 68
182, 68
U256
182, 68
182, 68
168, 55
156, 54
—
—
—
—
—
—
—
—
F324
—
—
—
215, 83
195, 61
—
—
—
—
—
—
—
F484
—
—
346, 140
—
331, 127
327, 135
295, 113
283, 106
294, 113
294, 113
226, 87
226, 87
U484
—
—
346, 140
—
331, 127
327, 135
295, 113
—
294, 113
294, 113
—
—
F780
—
—
—
—
535, 227
(6)
377, 163
429, 181
531, 233
429, 181
429, 181
429, 181
429, 181
94, 22
94, 22
84, 19
82, 18
—
—
—
—
—
—
—
—
160, 47 168, 55
148, 43 156, 54
128, 26
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
EP3CLS70
Cyclone III EP3CLS100
LS
EP3CLS150
EP3CLS200
Notes to
Table 1–2:
(1) For each device package, the first number indicates the number of the I/O pin; the second number indicates the differential channel count.
(2) For more information about device packaging specifications, refer to the Cyclone III
Package and Thermal Resistance
webpage.
(3) The I/O pin numbers are the maximum I/O counts (including clock input pins) supported by the device package combination and can be affected
by the configuration scheme selected for the device.
(4) All packages are available in lead-free and leaded options.
(5) Vertical migration is not supported between Cyclone III and Cyclone III LS devices.
(6) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/Os are restricted to 510 I/Os if you enable
migration to the EP3C120 and are using voltage referenced I/O standards. If you are not using voltage referenced I/O standards, you can increase
the maximum number of I/Os.
(7) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground
plane on your PCB. Use this exposed pad for electrical connectivity and not for thermal purposes.
(8) All Cyclone III device UBGA packages are supported by the Quartus II software version 7.1 SP1 and later, with the exception of the UBGA
packages of EP3C16, which are supported by the Quartus II software version 7.2.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
1–5
Table 1–3
lists Cyclone III device family package sizes.
Table 1–3. Cyclone III Device Family Package Sizes
Family
Package
E144
M164
P240
F256
Cyclone III
U256
F324
F484
U484
F780
F484
Cyclone III LS
U484
F780
Pitch (mm)
0.5
0.5
0.5
1.0
0.8
1.0
1.0
0.8
1.0
1.0
0.8
1.0
Nominal Area (mm
2
)
484
64
1197
289
196
361
529
361
841
529
361
841
Length x Width (mm
mm)
22
22
8
8
34.6
34.6
17
17
14
14
19
19
23 23
19
19
29
29
23
23
19
19
29
29
Height (mm)
1.60
1.40
4.10
1.55
2.20
2.20
2.60
2.20
2.60
2.60
2.20
2.60
Table 1–4
lists Cyclone III device family speed grades.
Table 1–4. Cyclone III Device Family Speed Grades (Part 1 of 2)
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
