SG5127FB212852QC2M
October 5, 2008
Ordering Information
Part Numbers
SG5127FB212852QC2M
Description
512Mx72 (4GB), DDR2, 240-pin Fully
Buffered DIMM, ECC, 128Mx8 Based,
PC2-5300, DDR2-667-555, 30.35mm,
Green Module (RoHS Compliant).
Label:
4GB 4Rx8 PC2-5300F-555-11-W_*
AMB Vendor
Device Vendor
IDT, Rev. L4
Qimonda, Rev. C2
AMB0780L4RJ8 HYB18T1G800C2F-3S
* This character defines PCB revision.
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SG5127FB212852QC2M
October 5, 2008
Revision History
• October 5, 2008
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SG5127FB212852QC2M
October 5, 2008
4GByte (512Mx72) DDR2 SDRAM Module - 128Mx8 Based
240-pin Fully Buffered DIMM, ECC
Features:
Device Speed
DDR2-667
CL (Device)
4.0/5.0
Cycle Time
3.0ns
Link Speed
4.0Gb/s
• AMB allows up to 8 DIMMs/Channel (288 devices) Trans-
parent Mode for DRAM Test
• MEMBIST and IBIST Test Functions
• V
DD
= V
DDQ
= 1.8V +/- 0.1V (for DDR2 SDRAM)
• V
CC
= 1.5V +/- 0.045V (for AMB)
• V
TT
= 0.9V +/- 0.036V (DRAM Interface Termination)
• V
DDSPD
= 3.3V +/- 0.3V
• Quad Rank Module (JEDEC Raw Card “W”)
• Lead Finish : Gold
• High-Speed differential PTP link between Controller & AMB
• SMBus Interface access to AMB Configuration Registers
FBD/AMB Specifications:
Fully Buffered DIMM (FBD) provides a high memory bandwidth, large capacity channel solution that has a narrow
host interface. Fully Buffered DIMMs use commodity DRAMs isolated from the channel behind a buffer (AMB) on
the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit den-
sity. Currently, FBD/AMB specification is broken-out into the following specifications:
1. FBD Design Specification: This specification defines the electrical and mechanical requirements for 240-pin,
PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-
Line Memory Modules (DDR2 SDRAM FBDs).
2. FBD Architecture and Protocol Specification: This specification covers Overview, Channel Initialization, Chan-
nel Protocol, and Reliability, Availability, and Serviceability (RAS) features of FBDIMM architecture.
3. FBD AMB Specification: The Advanced Memory Buffer allows buffering of memory traffic to support large
memory capacities. This specification covers information about various AMB interfaces (Channel/DRAM), Test
& Initialization functions, SMBus Interface, Clocking, Registers, etc.
4. FBD High-Speed Differential PTP Link Specification: This specification defines the high-speed differential
point-to-point signaling link for FB-DIMM, operating at the buffer supply voltage of 1.5V that is provided at the
FBDIMM connector. This specification also applies to FBD host chips which may operate with a different sup-
ply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The trans-
mitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and
transforms them into a serialized bit-stream.The link utilizes a derived clock approach and transmitter de-
emphasis to compensate for channel loss characteristics.
5. FBD SPD Specification: This specification describes the Serial Presence Detect (SPD) values for FBD.
6. FBD DFx Specification: The FB-DIMM DFx spec covers Design for Test (DFT), Design for Manufacturing
(DFM) and Design for Validation (DFV) requirements and implementation guidelines for Fully Buffered DIMM
technology.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SG5127FB212852QC2M
October 5, 2008
DDR2 240-Pin FB-DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID1
RESET#
V
SS
RFU
RFU
V
SS
PN0
PN0#
V
SS
PN1
PN1#
V
SS
PN2
PN2#
V
SS
Pin Pin
No. Name
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PN3
PN3#
V
SS
PN4
PN4#
V
SS
PN5
PN5#
V
SS
PN13
PN13#
V
SS
V
SS
RFU
RFU
V
SS
V
SS
PN12
PN12#
V
SS
PN6
PN6#
V
SS
PN7
PN7#
V
SS
PN8
PN8#
V
SS
PN9
Pin Pin
No. Name
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
PN9#
V
SS
PN10
PN10#
V
SS
PN11
PN11#
V
SS
V
SS
PS0
PS0#
V
SS
PS1
PS1#
V
SS
PS2
PS2#
V
SS
PS3
PS3#
V
SS
PS4
PS4#
V
SS
V
SS
RFU
RFU
V
SS
V
SS
PS9
Pin Pin
No. Name
91
92
93
94
95
96
97
98
99
PS9#
V
SS
PS5
PS5#
V
SS
PS6
PS6#
V
SS
PS7
Pin Pin
No. Name
121 V
DD
122 V
DD
123 V
DD
124 V
SS
125 V
DD
126 V
DD
127 V
DD
128 V
SS
129 V
CC
130 V
CC
131 V
SS
132 V
CC
133 V
CC
134 V
SS
135 V
TT
136 VID0
137 DNU/M_Test
138 V
SS
139 RFU
140 RFU
141 V
SS
142 SN0
143 SN0#
144 V
SS
145 SN1
146 SN1#
147 V
SS
148 SN2
149 SN2#
150 V
SS
Pin Pin
No. Name
151 SN3
152 SN3#
153 V
SS
154 SN4
155 SN4#
156 V
SS
157 SN5
158 SN5#
159 V
SS
160 SN13
161 SN13#
162 V
SS
163 V
SS
164 RFU
165 RFU
166 V
SS
167 V
SS
168 SN12
169 SN12#
170 V
SS
171 SN6
172 SN6#
173 V
SS
174 SN7
175 SN7#
176 V
SS
177 SN8
178 SN8#
179 V
SS
180 SN9
Pin Pin
No. Name
181 SN9#
182 V
SS
183 SN10
184 SN10#
185 V
SS
186 SN11
187 SN11#
188 V
SS
189 V
SS
190 SS0
191 SS0#
192 V
SS
193 SS1
194 SS1#
195 V
SS
196 SS2
197 SS2#
198 V
SS
199 SS3
200 SS3#
201 V
SS
202 SS4
203 SS4#
204 V
SS
205 V
SS
206 RFU
207 RFU
208 V
SS
209 V
SS
210 SS9
Pin Pin
No. Name
211 SS9#
212 V
SS
213 SS5
214 SS5#
215 V
SS
216 SS6
217 SS6#
218 V
SS
219 SS7
220 SS7#
221 V
SS
222 SS8
223 SS8#
224 V
SS
225 RFU
226 RFU
227 V
SS
228 SCK
229 SCK#
230 V
SS
231 V
DD
232 V
DD
233 V
DD
234 V
SS
235 V
DD
236 V
DD
237 V
TT
238 V
DDSPD
239 SA0
240 SA1
100 PS7#
101 V
SS
102 PS8
103 PS8#
104 V
SS
105 RFU
106 RFU
107 V
SS
108 V
DD
109 V
DD
110 V
SS
111
V
DD
112 V
DD
113 V
DD
114 V
SS
115 V
DD
116 V
DD
117 V
TT
118 SA2
119 SDA
120 SCL
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SG5127FB212852QC2M
October 5, 2008
Pin Description:
DIMM Connector Pin Description
Symbol
SCK
SCK#
PN0 ~ PN13
PN0# ~ PN13#
PS0 ~ PS9
PS0# ~ PS9#
SN0 ~ SN13
SN0# ~ SN13#
SS0 ~ SS9
SS0# ~ SS9#
SCL
SDA
SA0 ~ SA2
VID0 ~ VID1
Type
Input
Input
Output
Output
Input
Input
Input
Input
Output
Output
Input/Output
Input/Output
Input
Supply
Polarity
Positive Edge
Negative Edge
Positive Edge
Negative Edge
Positive Edge
Negative Edge
Positive Edge
Negative Edge
Positive Edge
Negative Edge
-
-
-
-
Function
Positive line of the differential pair of system clock inputs.
Negative line of the differential pair of system clock inputs.
Primary Northbound Data, positive lines.
Primary Northbound Data, negative lines.
Primary Southbound Data, positive lines.
Primary Southbound Data, negative lines.
Secondary Northbound Data, positive lines.
Secondary Northbound Data, negative lines.
Secondary Southbound Data, positive lines.
Secondary Southbound Data, negative lines.
Serial Presence Detect (SPD) for Clock Input.
SPD Data Input/Output.
SPD Address Inputs, also used to select the DIMM number in the AMB.
Voltage ID: These pins must be unconnected for DDR2-based Fully
Buffered DIMMs.
VID0 is V
DD
value: OPEN = 1.8V, GND = 1.5V;
VID1 is V
CC
value: OPEN = 1.5V, GND = 1.2V;
AMB Core Power and AMB Channel Interface Power(1.5 Volt).
DRAM Power and AMB DRAM I/O Power(1.8 Volt).
Ground.
DRAM Address/Command/Clock termination Power (V
DD
/2).
SPD Power (3.3 Volt).
Advanced Memory Buffer (AMB) reset signal.
Reserved for Future Use.
The DNU/M_Test pin provides an external connection for testing the
margin of V
REF
which is produced by a voltage divider on the module. It
is not intended to be used in normal system operation and must not
be connected (DNU) in a system.
V
CC
V
DD
V
SS
V
TT
V
DDSPD
RESET#
RFU
DNU/M_Test
Supply
Supply
Supply
Supply
Supply
Input
-
-
-
-
-
-
-
Active Low
-
-
Note: System Clock Signals (SCK & SCK#) switch at one-half the DRAM CK/CK# frequency.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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