external output matching circuit covers the entire 4.9-
5.9GHz band simultaneously. The external output match
allows for load line optimization for other applications or
optimized performance over narrower bands.
SZA-5044
4.9 – 5.9 GHz 5V Power Amplifier
4mm x 4mm QFN Package
•
•
•
•
•
•
•
•
Product Features
802.11a 54Mb/s Class AB Performance
Pout = 21.5dBm @ 3% EVM, 5V, 310mA
High Gain = 28dB
Output Return Loss < -11dB for Linear Tune
On-chip Output Power Detector
P1dB = 29dBm @ 5V
Simultaneous 4.9- 5.9GHz Performance
Robust - Survives RF Input Power = +15dBm
Power up/down control < 1µs, Vpc 2.9V to 5V
Functional Block Diagram
Vcc
Pow er
Up/Dow n
Control
Activ e
Bias
Activ e
Bias
Activ e
Bias
RFIN
RFOUT
Applications
Pow er Detector
Vout
Key Specifications
Symbol
f
O
P
1dB
S
21
Pout
NF
IRL
ORL
Vdet Range
Icq
I
VPC
R
th, j-l
Parameters: Test Conditions, App circuit page 4
Z
0
= 50Ω, V
CC
= 5.0V, Icq = 220mA, T
BP
= 25ºC
Frequency of Operation
Output Power at 1dB Compression – 5.15 GHz
Output Power at 1dB Compression – 5.875 GHz
Gain at 5.15 GHz
Gain at 5.875 GHz
•
•
•
802.11a WLAN, OFDM
5.8GHz ISM Band
Fixed Wireless, UNII, 802.16 WiMAX
Unit
MHz
dBm
dB
dBm
dB
dB
V
mA
mA
ºC/W
185
10
7
Min.
4900
28.0
26.5
27.2
24.4
29.5
28.0
29.2
26.4
22
21
6.3
15
11
0.8 to 1.9
220
1.7
24
255
31.2
28.4
Typ.
Max.
5900
Output power at 3% EVM 802.11a 54Mb/s - 5.15GHz
Output Power at 3% EVM 802.11a 54Mb/s - 5.875GHz
Noise Figure at 5.875 GHz
Worst Case Input Return Loss 5.15-5.875GHz
Worst Case Output Return Loss 5.15-5.875GHz
Output Voltage Range for Pout=10dBm to 26dBm
Vcc Quiescent Current
Power Up Control Current, Vpc=5V ( I
VPC1
+ I
VPC2
+ I
VPC3
)
Thermal Resistance (junction - lead)
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product
for use in life-support devices and/or systems.
Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
EDS-103585 Rev C
Preliminary
SZA-5044 4.9-5.9 GHz Power Amp
Pin Out Description
Pin #
1,3,5,9,
11,15,17
6
Function
N/C
Description
Pins are not used. May be grounded, left open, or connected to adjacent pin.
VPC1 is the bias control pin for the stage 1 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
VPC2 is the bias control pin for the stage 2 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
VPC3 is the bias control pin for the stage 3 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.
RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be
used for proper operation.
RF output pin. This is also another connection to the 3rd stage collector
3rd stage collector bias pin. Apply 5V to this pin.
2nd stage collector bias pin. Apply 5V to this pin.
1st stage collector bias pin. Apply 5V to this pin.
Active bias network VCC. Apply 5V to this pin.
Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for
optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-
ommended land pattern (page 5).
VPC1
7
VPC2
8
10
2,4
12,13,14
16
18
19
20
EPAD
VPC3
Vdet
RFIN
RFOUT
VC3
VC2
VC1
Vbias
Gnd
Simplified Device Schematic
Pin
6
Pin
20
Pin
19
Pin
7
Pin
18
Pin
8
Pin
16
Absolute Maximum Ratings
Parameters
VC3 Collector Bias Current (pin16)
VC2 Collector Bias Current (pin18)
VC1 Collector Bias Current (pin19)
Device Voltage (V
D
)
Value
500
225
75
7.0
3.4
-40 to +85
15
2
-40 to +150
+150
>1000
Unit
mA
mA
mA
V
W
ºC
dBm
dBm
ºC
ºC
V
Stage 1
Bias
Stage 2
Bias
Stage 3
Bias
Pin 12,13,14
Power Dissipation
Operating Lead Temperature (T
L
)
RF Input Power for 50 ohm RF out load
RF Input Power for 10:1 VSWR RF out
load
Storage Temperature Range
Operating Junction Temperature (T
J
)
ESD Human Body Model
Pin 2, 4
EPAD
EPAD
Pin
10
EPAD
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Bias conditions should also satisfy the following expression:
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