MX26L12711MC
128M [x16] SINGLE 3V PAGE MODE MTP MEMORY
FEATURES
• 3.0V to 3.6V operation voltage
• 128Mb density with two banks controled by BE0, BE1
• Block Structure
- 64 x 64Kword Erase Blocks for each bank
• Fast random / page mode access time
- 100/30 ns Read Access Time (page depth:8-word)
• 16-Word Write Buffer
- 14 us/word Effective Programming Time
• High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 10 cycles
Packaging
- 44-Lead SOP
Performance
• Low power dissipation
- typical 15mA active current for page mode read
- 160uA/(max.) standby current
Technology
- Two bits per cell Nbit (0.25u) MTP Technology
GENERAL DESCRIPTION
The MXIC's MX26L12711MC MTP use the most advance
2 bits/cell Nbit technology, double the storage capacity
of memory cell. The device provide the high density MTP
memory solution with reliable performance and most cost-
effective.
The device organized as by 16 bits of output bus. The
device is packaged in 44-Lead SOP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
electrical erasure and programming. The device uses a
command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0986
REV. 1.0, OCT. 29, 2003
1
MX26L12711MC
Table 1. Bus Operations
Mode
Read Array
Output Disable
Bank0
Stabdby
Bank1
Bank 0,1
Bank0
Read Identifier
Codes/OTP
Read Query
Bank1
Inhibited
Bank0
Bank1
Inhibited
Bank0
Read Status
(WSM Off)
Read Status
(WSM On)
Write
Bank1
Inhibited
Bank0
Bank1
Inhibited
Bank0
Bank1
Inhibited
5
5
Bank0
Bank1
Inhibited
Notes
4
BE0
VIL
VIH
VIL
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
BE1
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIH
X
N/A
D7=DOUT
D18-8=High Z
Q6-0=High Z
DIN
N/A
VIL
VIH
See
Table 5
N/A
DOUT
VIL
VIH
VIH
X
VIH
X
X
X
See
Table 13
OE
VIL
WE
VIH
Address
X
N/A
High Z
High Z
See Table 13
Note 5
N/A
Note 6
DQ0-15
DOUT
VIL
VIH
X
7,8
VIH
VIL
X
NOTES:
1. OE and WE should never be enabled simultaneously.
2. Q refers to Q0~Q15.
3. X can be VIL or VIH for control and address pins.
4. High Z will be VOH with an external pull-up resistor.
5. See Section , "Read Identifier Codes" for read identifier code data.
6. See Section , "Read Query Mode Command" for read query data.
7. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VCC is
within specification.
8. Refer to Table 2 on page 7 for valid DIN during a write operation.
P/N:PM0986
REV. 1.0, OCT. 29, 2003
5