W185
Six Output Peak Reducing EMI Solution
Features
•
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread output of Reference input
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 24-pin SSOP (Shrink Small Outline
Package)
• Outputs may be selectively disabled
Table 1. Modulation Width Selection
SS%
0
1
W185
Output
F
in
≥
F
out
≥
F
in
– 1.25%
F
in
≥
F
out
≥
F
in
– 3.75%
W185-5
Output
F
in
+ 0.625%
≥
F
in
≥
– 0.625%
F
in
+ 1.875%
≥
F
in
≥
–1.875%
Table 2. Frequency Range Selection
FS2
0
0
1
FS1
0
1
0
1
Frequency Range
28 MHz
≤
F
IN
≤
38 MHz
38 MHz
≤
F
IN
≤
48 MHz
46 MHz
≤
F
IN
≤
60 MHz
58 MHz
≤
F
IN
≤
75 MHz
Key Specifications
Supply Voltages: ........................................... V
DD
= 3.3V±5%
or V
DD
= 5V±10%
Frequency Range: ............................ 28 MHz
≤
F
in
≤
75 MHz
Crystal Reference Range:................. 28 MHz
≤
F
in
≤
40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
1
Table 3. Output Enable
EN1
0
0
1
1
EN2
0
1
0
1
Low
Low
Active
Active
CLK0:4
Low
Active
Low
Active
CLK5
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SSOP
X1
XTAL
Input
40MHz
max.
X2
W185
Spread Spectrum
Output
(EMI suppressed)
REFOUT
FS2
X1
X2
GND
SS%
EN2
GND
CLK0
VDD
CLK1
CLK2
1
2
3
4
5
6
24
23
22
21
20
19
18
17
16
15
14
13
SSON#
RESET
FS1
VDD
VDD
NC
EN1
CLK5
VDD
CLK4
GND
CLK3
W185/W185-5
7
8
9
3.3V or 5.0V
10
11
12
Oscillator or
Reference Input
W185
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 25, 2000, rev. *A
W185
Pin Definitions
Pin Name
CLK0:5
CLKIN or X1
Pin No.
9, 11, 12, 13,
15, 17
3
Pin
Type
O
I
Pin Description
Modulated Frequency Outputs:
Frequency modulated copies of the unmod-
ulated input clock (SSON# asserted).
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
Crystal Connection:
If using an external reference, this pin must be left un-
connected.
Modulation Width Selection:
When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistor.
Modulation Profile Restart:
A rising edge on this input restarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
Non-Modulated Output:
This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
Output Enable Select Pins:
These pins control the activity of specific output
buffers. See
Table 3
on page 1.
Spread Spectrum Control (Active LOW):
Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
Frequency Selection Bit 1 and 2:
These pins select the frequency of opera-
tion. Refer to
Table 1.
These pins have internal pull-up resistors.
Power Connection:
Connected to 3.3V or 5V power supply.
Ground Connection:
This should be connected to the common ground plane.
No Connect:
This pin should be left floating.
NC or X2
SS%
4
6
I
I
Reset
23
I
REFOUT
1
O
EN1:2
SSON#
18, 7
24
I
I
FS1:2
VDD
GND
NC
22, 2
10, 16, 20, 21
5, 8, 14
19
I
P
G
NC
2
W185
Overview
The W185 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
times the reference frequency. (Note: For the W184 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage may be selected as either
1.25% or 3.75% (see
Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
Functional Description
The W185 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in
Figure 1.
The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
V
DD
Clock Input
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Reference Input
Σ
VCO
Post
Dividers
CLKOUT
(EMI suppressed)
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
3
W185
Spread Spectrum Frequency Timing
Generation
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in
)LJXUH
.
As shown in
)LJXUH
, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where
P
is the percentage of deviation and
F
is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
)LJXUH
. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions.
)LJXUH
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN.
Figure 3. Typical Modulation Profile
4
100%
W185
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
DC Electrical Characteristics
:
0°C < T
A
< 70°C, V
DD
= 3.3V ±5%
Parameter
I
DD
t
ON
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
R
P
Z
OUT
Description
Supply Current
Power Up Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
500
25
Note 1
Note 1
@ 0.4V, V
DD
= 3.3V
@ 2.4V, V
DD
= 3.3V
15
15
7
2.4
–50
50
2.4
0.4
First locked clock cycle after Power
Good
Test Condition
Min.
Typ.
18
Max.
32
5
0.8
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
kΩ
Ω
Note:
1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
5
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