INTEGRATED CIRCUITS
DATA SHEET
SAA2032
Digital equalization for the tape
drive processing of the DCC system
Product specification
Supersedes data of February 1993
File under Integrated Circuits, Miscellaneous
February 1995
Philips Semiconductors
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
FEATURES
•
Analog-to-digital conversion, demultiplexing,
equalization and zero crossing of time multiplexed
analog read amplifier signal
•
Microcontroller interface
•
Search mode envelope, label and virgin detection of the
AUX channel
•
Search mode tape speed measurement
•
Simplified external biassing
•
Reduced power consumption
•
Analog eye output
•
4 V nominal operating voltage capability.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA2032GP
Note
PACKAGE
PINS
44
PIN POSITION
QFP 1
MATERIAL
plastic
GENERAL DESCRIPTION
SAA2032
Performing the Digital Equalizing function in the Digital
Compact Cassette (DCC) system, the SAA2032 is
intended for use in conjunction with the SAA2022, read
amplifier TDA1317 or TDA1318.
CODE
SOT205AG
1. When using reflow soldering it is recommended that the Dry Packing instructions in the
Quality Reference Pocketbook
are followed. The pocketbook can be ordered using the code 9398 510 34011.
February 1995
2
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SAA2032
VDDAD
VDD
11
43
12
3
RDCLK
RDSYNC
LABEL
VIRGIN
AENV
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
f 24
CLOCK
GENERATION
2
37
SAA2032
VIRGIN
LABEL
DETECTOR
36
38
22
23
24
25
26
27
28
29
30
VIN
5
ADC
DEMUX
FILTER
SLICER
1
44
15
DIGEYE
VAL
ANEYE
DAC
32
33
34
35
LT
INTERFACE
LTENDEQ
LTCNT1
LTCNT0
LTCLK
31
LTDATA
8, 14
10
13, 17, 39
MEA663
V SSA
V SSAD
V SS
Fig.1 Block diagram.
February 1995
3
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
PINNING
SYMBOL
DIGEYE
RDSYNC
RDCLK
TEST1
VIN
REFN
REFP
V
SSA
BIASA
V
SSAD
V
DDAD
V
DD
V
SS
V
SSA
ANEYE
n.c.
V
SS
TEST4
TEST5
TEST6
TEST7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX
LTDATA
LTENDEQ
LTCNT1
LTCNT0
LTCLK
VIRGIN
LABEL
AENV
V
SS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
serial data output for eye pattern
SYNC data for Read Amplifier (push-pull output)
data clock for Read Amplifier (push-pull output)
test 1; to be connected to V
SS
analog time multiplexed input from Read Amplifier
lower reference voltage (+1 V) for ADC
upper reference voltage (+3.1 V) for ADC
analog ground (0 V)
bias current for ADC (sinks current from V
DDAD
via 33 kΩ)
supply ground (0 V) for ADC
supply voltage (+5 V) for ADC
supply voltage (+5 V)
supply ground (0 V)
supply ground (0 V)
analog eye voltage output
not connected
supply ground (0 V)
test 4; do not connect
test 5; do not connect
test 6; do not connect
test 7; do not connect
DESCRIPTION
SAA2032
channel 0 output for SAA2022 (DCC Drive Signal Processing) (push-pull output)
channel 1 output for SAA2022 (push-pull output)
channel 2 output for SAA2022 (push-pull output)
channel 3 output for SAA2022 (push-pull output)
channel 4 output for SAA2022 (push-pull output)
channel 5 output for SAA2022 (push-pull output)
channel 6 output for SAA2022 (push-pull output)
channel 7 output for SAA2022 (push-pull output)
AUX channel output for SAA2022 (push-pull output)
microcontroller I/O data interface (3-state push-pull output and input; CMOS levels)
microcontroller interface enabling (CMOS input levels)
microcontroller interface; mode control 1 (CMOS input levels)
microcontroller interface; mode control 0 (CMOS input levels)
microcontroller bit-clock interface (CMOS input levels)
search mode virgin detection output
search mode label detection output
search mode auxiliary detection output
supply ground (0 V)
February 1995
4
Philips Semiconductors
Product specification
Digital equalization for the tape
drive processing of the DCC system
SYMBOL
TEST8
TEST9
TEST10
f24
VAL
PIN
40
41
42
43
44
test 8 input; to be connected to V
SS
test 9 input; to be connected to V
SS
test 10 input; to be connected to V
SS
clock input; typical frequency 24.576 MHz (CMOS input)
synchronization output for DIGEYE
DESCRIPTION
SAA2032
44
43
42
41
40
39
38
37
36
35
34
LTCNT0
TEST10
VIRGIN
LABEL
TEST9
TEST8
AENV
VSS
VAL
LTCLK
f24
DIGEYE
RDSYNC
RDCLK
TEST1
VIN
REFN
REFP
V
SSA
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
LTCNT1
LTENDEQ
LTDATA
AUX
CH7
CH6
CH5
CH4
CH3
CH2
CH1
SAA2032
28
27
26
25
24
23
BIASA
VSSAD
VDDAD
15
16
18
20
12
13
14
17
19
21
22
VSS
VSSA
ANEYE
n.c.
V SS
TEST4
TEST5
TEST6
Fig.2 Pin configuration.
February 1995
5
TEST7
V DD
CH0
MEA661
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