INTEGRATED CIRCUITS
DATA SHEET
SAA7207H
Reed Solomon decoder IC
Product specification
File under Integrated Circuits, IC02
1996 Jul 17
Philips Semiconductors
Product specification
Reed Solomon decoder IC
FEATURES
•
(204, 188 and 17) Digital Video Broadcasting (DVB)
compliant Reed Solomon (RS) codes
•
Automatic synchronization of bytes, blocks and frame
•
Convolutional de-interleaving (I = 12)
•
Energy dispersal de-randomizing
•
Contained in a 44-pin quad flat package
•
I
2
C-bus interface
•
6 quasi-bidirectional ports
•
Boundary scan facility.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD(tot)
T
CLK
total supply current
input clock period
PARAMETER
operational supply voltage
−
−
MIN.
4.75
TYP.
5.00
65
31.5
APPLICATIONS
SAA7207H
•
Forward Error Correction (FEC) for digital TV
distribution according to the DVB standard.
MAX.
5.25
−
−
V
UNIT
mA
ns
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7207H/C1
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
VERSION
SOT307-2
1996 Jul 17
2
Philips Semiconductors
Product specification
Reed Solomon decoder IC
BLOCK DIAGRAM
SAA7207H
handbook, full pagewidth
CLK
38
DATA1
DATA0
VALI
TRST
TCK
TMS
TDI
TDO
TC0
TC1
35
36
34
3
4
5
6
7
41
42
RAM D
INPUT
INTERFACE
TEST
CONTROL BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
1/2CLK
VALI
DATA (0 : 3)
2
SYNCHRONIZATION
NOSYNC
1/4CLK
DATA (7 : 0)
DE-INTERLEAVING
1/4CLK
SYNDROME
CALCULATION
DATA (7 : 0)
RAM B
BUFFER
RAM M
syndrome
coefficient
ERROR
CORRECTION
1/4CLK
SDA
SCL
PORT5
to
PORT0
44
1
I
2
C-BUS
INTERFACE
1/4CLK
27 to 32
OUTPUT
INTERFACE
DESCRAMBLER
DATA (7 : 0)
21
RESET
43
OE
DATA (7 : 0)
11, 12, 13, 15,
16,17,19, 20,
9
BYTEO0
to
BYTEO7
BCLK
BEGIN
BERR
SAA7207H
10, 18, 25,
33, 39
24
23
VDD
8, 14, 22,
26, 37, 40
VSS
MBH315
Fig.1 Block diagram.
1996 Jul 17
3
Philips Semiconductors
Product specification
Reed Solomon decoder IC
PINNING
SYMBOL
SCL
NOSYNC
TRST
TCK
TMS
TDI
TDO
V
SS
BCLK
V
DD
BYTEO0
BYTEO1
BYTEO2
V
SS
BYTEO3
BYTEO4
BYTEO5
V
DD
BYTEO6
BYTEO7
OE
V
SS
BERR
BEGIN
V
DD
V
SS
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
V
DD
VALI
DATA1
DATA0
V
SS
CLK
V
DD
V
SS
1996 Jul 17
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
I
O
I
I
I
I
O
−
O*
(1)
−
O*
(1)
O*
(1)
O*
(1)
−
O*
(1)
O*
(1)
O*
(1)
−
O*
(1)
O*
(1)
I
−
O*
(1)
O*
(1)
−
−
I/O
I/O
I/O
I/O
I/O
I/O
−
I
I
I
−
I
−
−
serial clock input (I
2
C-bus)
not synchronized output (1 = not synchronized)
boundary scan test reset (0 = active)
boundary scan test clock
boundary scan test mode select (1 = BST select)
boundary scan test data input
boundary scan test data output
ground
byte clock output
positive supply voltage
output data byte 0 (LSB)
output data byte 1
output data byte 2
ground
output data byte 3
output data byte 4
output data byte 5
positive supply voltage
output data byte 6
output data byte 7 (MSB)
DESCRIPTION
SAA7207H
output enable not (active LOW; 1 = O*
(1)
high impedance)
ground
block error output (1 = uncorrectable block)
begin of block output (1st byte of block is output)
positive supply voltage
ground
quasi-bidirectional port 5
quasi-bidirectional port 4
quasi-bidirectional port 3
quasi-bidirectional port 2
quasi-bidirectional port 1
quasi-bidirectional port 0
positive supply voltage
valid input (1 = data is valid)
input data 1 (MSB)
input data 0 (LSB)
ground
master clock input (also acting as input data clock)
positive supply voltage
ground
4
Philips Semiconductors
Product specification
Reed Solomon decoder IC
SAA7207H
SYMBOL
TC0
TC1
RESET
SDA
Note
PIN
41
42
43
44
I/O
I
I
I
I/O
DESCRIPTION
test mode control input 0 (0 = application mode)
test mode control input 1 (0 = application mode)
master reset input (1 = active)
bidirectional serial data port (I
2
C-bus)
1. When OE is active (pin 21 = HIGH), all O* outputs become high impedance.
43 RESET
36 DATA0
35 DATA1
handbook, full pagewidth
34 VALI
39 VDD
44 SDA
40 VSS
37 VSS
38 CLK
42 TC1
41 TC0
SCL
NOSYNC
TRST
TCK
TMS
TDI
TDO
VSS
BCLK
1
2
3
4
5
6
7
8
9
33 VDD
32 PORT0
31 PORT1
30 PORT2
29 PORT3
SAA7207H
28 PORT4
27 PORT5
26 VSS
25 VDD
24 BEGIN
23 BERR
VDD 10
BYTEO0 11
BYTEO1 12
BYTEO2 13
VSS 14
BYTEO3 15
BYTEO4 16
BYTEO5 17
VDD 18
BYTEO6 19
BYTEO7 20
OE 21
VSS 22
MBH314
Fig.2 Pin configuration.
1996 Jul 17
5
PCB设计
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