Philips Semiconductors
Product specification
Audio Digital Input Circuit (ADIC)
GENERAL DESCRIPTION
SAA7274
The SAA7274 is an Audio Digital Input Circuit (ADIC) which converts digital audio signals in accordance with the
IEC/EBU standards, IEC tech. com. No. 84, secr. 50, Jan. 1987 into an equivalent binary value of data and control bits.
The output function of this device is to convert the equivalent binary value of data bits (for each channel) into a serial
digital audio signal which conforms to the I
2
S format.
Features
•
I
2
S bus output
•
Biphase audio signal (Satellite radio, compact disc and DAT)
QUICK REFERENCE DATA
PARAMETER
Supply
Supply voltage range
Inputs
Input voltage HIGH
Input voltage LOW
Input current
Input capacitance
Outputs
Output voltage HIGH
Output voltage LOW
Operating ambient
temperature range
PACKAGE OUTLINES
SAA7274P: 24-lead DIL; plastic (SOT101A); SOT101-1; 1996 September 05.
SAA7274T: 24-lead mini-pack; plastic (SO24; SOT137A); SOT137-1; 1996 September 05.
T
amb
−40
−
+70
°C
V
OH
V
OL
V
DD
−0.5
−
−
−
−
0.4
V
V
V
I
= 0 V
V
I
= 5.5 V
except IBIFA
V
IH
V
IL
−I
I
I
I
C
I
0.7 V
DD
0
−
−
−
−
−
−
−
4
V
DD
0.3 V
DD
1
1
6
V
V
µA
µA
pF
V
DD
4.5
−
5.5
V
CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
July 1991
2
Philips Semiconductors
Product specification
Audio Digital Input Circuit (ADIC)
PINNING
Power supply
V
DD
V
SS
IBIFA
IFDEN
IPHEN
positive supply voltage (5 V)
ground (0 V)
SAA7274
Inputs (CMOS protection)
biphase input signal (min. 1 MHz;
max. 3.1 MHz)
frequency detector enable
phase-locked loop edge selector
ITEST1 test input enable
ITEST2 test input enable
IDACL
IWSEL
IDOEN
IOSCL
data clock input signal (max. 5 MHz)
word select input signal (max. 50 kHz)
output enable
clock oscillator input (min. 8 MHz;
max. 12.5 MHz)
Outputs (CMOS push-pull)
OCDB
OLOC
OREF
OPHA
OPRE
OSCU
OSDU
OSCL
OOSC
control data bits (max. 400 kHz)
out-of-lock signal
phase reference signal (max. 6.2 MHz)
phase output signal (max. 6.2 MHz)
pre-emphasis level
user clock/copy-bit signal (max. 3.1 MHz)
user data/pre-emphasis (max. 3.1 MHz)
system clock output (min. 8 MHz;
max. 12.5 MHz)
clock oscillator output (min. 8 MHz;
max. 12.5 MHz)
Fig.2 Pinning diagram.
Outputs (3-state push-pull)
OBSY
OWSY
ODCL
OSDA
block synchronization output signal
(1/49152 system clock)
word clock output signal (1/256 system clock)
data clock output signal (1/4 system clock)
data output signal (max. 2.5 MHz)
July 1991
4
Philips Semiconductors
Product specification
Audio Digital Input Circuit (ADIC)
FUNCTIONAL DESCRIPTION
Main function
SAA7274
The biphase input signal must conform to the IEC/EBU standards, IEC tech. com. No. 84, secr. 50, Jan. 1987 format,
as well as satisfying the following conditions:
•
number of channels: 2
•
transmission code: biphase mark
•
synchronization method: biphase violation
•
number of data bits: 24, starting with the LSB
•
number of control bits: 4
•
preamble values:
Table 1
Preamble values
0
11101000
1
00010111
preceding cell
block preamble
The main function performs the following tasks:
•
Provides the output function with the equivalent binary value of the data bits separately for each of the two channels.
These values are available until new information is received.
•
Generates an out-of-lock output signal (OLOC) which is HIGH when the frequency of the biphase input signal is equal
to 1/4 of the system clock frequency and when the block preambles are detected in the biphase input signal.
•
If the biphase input signal is not present after 32 clock pulses and also whenever the biphase input signal and IOSCL/4
drift away from each other by more than 32 clock pulses, then the output OSCU is forced HIGH and output OSDU,
OPRE, OLOC, OCDB and OSDA are forced LOW.
•
Generates a data clock output signal (ODCL) with a frequency of 1/4 of the system clock. When a block preamble is
detected in the biphase input signal ODCL is synchronized to a LOW value.
•
Generates a word clock output signal (OWSY) with a frequency of 1/256 of the system clock. When a block preamble
is detected in the biphase input signal OWSY is synchronized to a LOW value.
•
Generates a block synchronization output signal (OBSY). This signal is HIGH during 4 system clock periods and has
a frequency of 1/49152 of the system clock. The signal is synchronized with the block preambles of the biphase input
signal.
•
Generates a phase output signal (OPHA) and a phase reference signal (OREF). If the frequency of the biphase input
signal (IBIFA) equals 1/4 of the system clock frequency (f
IOSCL
/4) then the IC generates OPHA and OREF as shown
in Fig.3.
If the frequency of the biphase input signal (IBIFA) is greater or less than 1/4 of the system clock frequency then the
IC generates OPHA and OREF as shown in Fig.4.
July 1991
5
嵌入式系统
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