INTEGRATED CIRCUITS
DATA SHEET
SAA7373
Digital servo processor and
Compact Disc decoder (CD7)
Product specification
File under Integrated Circuits, IC01
1998 Jul 06
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.5.3
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8
7.9
7.9.1
7.10
7.11
7.12
7.13
7.13.1
7.13.3
7.13.4
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Decoder part
Principle operational modes of the decoder
Decoding speed and crystal frequency
Lock-to-disc mode
Standby modes
Crystal oscillator
Data slicer and clock regenerator
Demodulator
Frame sync protection
EFM demodulation
Subcode data processing
Q-channel processing
EIAJ 3 and 4-wire subcode (CD graphics)
interface
V4 subcode interface
FIFO error corrector
Flags output (CFLG)
C2FAIL
Audio functions
De-emphasis and phase linearity
Digital oversampling filter
Concealment
Mute, full-speed, attenuation and fade
Peak detector
DAC interface
EBU interface
Format
KILL circuit
Audio features off
The VIA interface
Spindle motor control
Motor output modes
Loop characteristics
FIFO overflow
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.5
7.14.6
7.14.7
7.14.8
7.14.9
7.15
7.15.1
7.15.2
7.15.3
7.15.4
7.15.5
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
18
SAA7373
Servo part
Diode signal processing
Signal conditioning
Focus servo system
Radial servo system
Off-track counting
Defect detection
Off-track detection
High level features
Driver interface
Microcontroller interface
Microprocessor interface (4-wire bus mode)
Microcontroller interface (I
2
C-bus mode)
Summary of functions controlled by
registers 0 to F
Summary of servo commands
Summary of servo command parameters
LIMITING VALUES
OPERATING CHARACTERISTICS
OPERATING CHARACTERISTICS
(SUBCODE INTERFACE TIMING)
OPERATING CHARACTERISTICS
(I
2
S-BUS TIMING)
OPERATING CHARACTERISTICS
(MICROCONTROLLER INTERFACE TIMING)
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1998 Jul 06
2
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
1
FEATURES
SAA7373
•
CD ROM mode
•
Single and double-speed modes
•
Lock-to-disc mode
•
Full error correction strategy, t = 2 and e = 4
•
Full CD graphics interface
•
All standard decoder functions implemented digitally on
chip
•
FIFO overflow concealment for rotational shock
resistance
•
Digital audio interface (EBU), audio and data
•
2 and 4 times oversampling integrated digital filter,
including f
s
mode
•
Audio data peak level detection
•
Kill interface for DAC deactivation during digital silence
•
All TDA1301 (DSIC2) digital servo functions, plus extra
high-level functions
•
Low focus noise
•
Improved playability on ABEX TCD-721R, TCD-725 and
TCD-714 discs
•
Automatic closed loop gain control available for focus
and radial loops
•
Pulsed sledge support
3
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
f
xtal
T
amb
T
stg
4
PARAMETER
supply voltage
supply current
crystal frequency
operating ambient temperature
storage temperature
n = 1 mode
CONDITIONS
3.4
−
8
−40
−55
MIN.
TYP.
5.0
49
8.4672
−
−
−
35
+85
+125
MAX.
5.5
V
mA
MHz
°C
°C
UNIT
•
Microcontroller loading LOW
•
High-level servo control option
•
High-level mechanism monitor
•
Communication may be via TDA1301/SAA7345
compatible bus or I
2
C-bus
•
On-chip clock multiplier allows the use of 8.4672 MHz
crystal.
2
GENERAL DESCRIPTION
The SAA7373 is a single chip combining the functions of a
CD decoder IC and digital servo IC. The decoder part is
based on the SAA7345 (CD6) with an improved error
correction strategy. The servo part is based on the
TDA1301T (DSIC2) with improvements incorporated,
extra features have also been added.
Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
Compact Disc application.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP64
DESCRIPTION
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14
×
14
×
2.7 mm
VERSION
SOT393-1
SAA7373GP
1998 Jul 06
3
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
5
BLOCK DIAGRAM
VSSA2 VDDA1 VSSD1 VSSD3 VDDD1(P) VDDD3(C)
IrefT VSSA1 VSSA3 VDDA2 VSSD2 VSSD4 VDDD2(P)
D4
7
10
1
12
16
2
19
32
39
49
56
30
47
59
SAA7373
handbook, full pagewidth
VRL D1 D2
6
3
4
D3
5
R1
R2
8
9
ADC
PRE-
PROCESSING
CONTROL
FUNCTION
OUTPUT
STAGES
26
27
28
RA
FO
SL
VRH
11
Vref
GENERATOR
CONTROL
PART
SCL
SDA
RAB
SILD
52
51
53
54
MICROCONTROLLER
INTERFACE
64
LDON
SAA7373
DIGITAL
PLL
FRONT END
33
MOTOR
CONTROL
34
HFIN
HFREF
ISLICE
Iref
15
17
14
18
EFM
DEMODULATOR
TEST
ERROR
CORRECTOR
FLAGS
SRAM
60
AUDIO
PROCESSOR
RAM
ADDRESSER
EBU
INTERFACE
31
61
CFLG
MOTO1
MOTO2
TEST1
TEST2
TEST3
20
23
29
SELPLL
CRIN
CROUT
CL16
CL11
CL4
13
21
22
24
25
50
TIMING
C2FAIL
DOBM
SBSY
SFSY
SUB
RCK
35
36
38
37
SUBCODE
PROCESSOR
PEAK
DETECT
48
DECODER
MICRO-
CONTROLLER
INTERFACE
46
SERIAL DATA
INTERFACE
VERSATILE PINS
INTERFACE
KILL
45
44
SCLK
WCLK
DATA
EF
STATUS
58
RESET
57
62
63
42
41
40
43
MGR321
V1
V2
V3
V4
V5
KILL
Fig.1 Block diagram.
1998 Jul 06
4
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
6
PINNING
SYMBOL
V
SSA1
V
DDA1
D1
D2
D3
V
RL
D4
R1
R2
I
refT
V
RH
V
SSA2
SELPLL
ISLICE
HFIN
V
SSA3
HFREF
I
ref
V
DDA2
TEST1
CRIN
CROUT
TEST2
CL16
CL11
RA
FO
SL
TEST3
V
DDD1(P)
DOBM
V
SSD1
MOTO1
MOTO2
SBSY
SFSY
RCK
SUB
V
SSD2
V5
1998 Jul 06
PIN
1
(1)
2
(1)
3
4
5
6
7
8
9
10
11
12
(1)
13
14
15
16
(1)
17
18
19
(1)
20
21
22
23
24
25
26
27
28
29
30
(1)
31
32
(1)
33
34
35
36
37
38
39
(1)
40
analog ground 1
analog supply voltage 1
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
reference voltage input for ADC
unipolar current input (central diode signal input)
unipolar current input (satellite diode signal input)
unipolar current input (satellite diode signal input)
current reference output for ADC calibration
reference voltage output from ADC
analog ground 2
selects whether internal clock multiplier PLL is used
current feedback output from data slicer
comparator signal input
analog ground 3
comparator common mode input
reference current output pin (nominally 0.5V
DD
)
analog supply voltage 2
test control input 1; this pin should be tied LOW
crystal/resonator input
crystal/resonator output
test control input 2; this pin should be tied LOW
16.9344 MHz system clock output
11.2896 or 5.6448 MHz clock output (3-state)
radial actuator output
focus actuator output
sledge control output
test control input 3; this pin should be tied LOW
digital supply voltage 1 for periphery
bi-phase mark output (externally buffered; 3-state)
digital ground 1
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
subcode block sync output (3-state)
subcode frame sync output (3-state)
subcode clock input
P-to-W subcode output bits (3-state)
digital ground 2
versatile output pin 5
5
DESCRIPTION
SAA7373
嵌入式系统
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