IS43/46LR32800F
2M
x
32Bits
x
4Banks Mobile DDR SDRAM
Description
The IS43/46LR32800F is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x
32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 32-bit bus. The double data rate architecture is essentially a 2
N
prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• 64ms refresh period (4K cycle)
• Auto & self refresh
• Concurrent Auto Precharge
• Maximum clock frequency up to 200MHZ
• Maximum data rate up to 400Mbps/pin
• Power Saving support
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength,
or 3/4, 1/2, 1/4, 1/8 of Full Strength
• Status Register Read (SRR)
• LVCMOS compatible inputs/outputs
• Packages:
- 90-Ball FBGA
- 152-Ball PoP BGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | February 2013
www.issi.com
- dram@issi.com
1
IS43/46LR32800F
Table2 : Pin Descriptions
Symbol
Type
Function
Descriptions
The system clock input. CK and /CK are differential clock
inputs. All address and control input signals are registered on
the crossing of the rising edge of CK and falling edge of /CK.
Input and output data is referenced to the crossing of CK and
/CK.
CKE is clock enable controls input. CKE HIGH activates, and
CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. CKE is synchronous for all functions
except for SELF REFRESH EXIT, which is achieved
asynchronously.
/CS enables (registered Low) and disables (registered High)
the command decoder. All commands are masked when /CS
IS REGISTERED high. /CS provides for external bank selection
on systems with multiple banks. /CS is considered part of the
command code.
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standard mode register or
extended mode register) is loaded during a LOAD MODE
REGISTER command.
Row Address
Column Address
Auto Precharge
: RA0~RA11
: CA0~CA8
: A10
CK, /CK
Input
System Clock
CKE
Input
Clock Enable
/CS
Input
Chip Select
BA0, BA1
Input
Bank Address
A0~A11
Input
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
/RAS, /CAS, /WE
Input
/RAS, /CAS and /WE define the operation.
Refer function truth table for details.
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM balls are input-only.
DM0~DM3
Input
Data Input Mask
DQ0~DQ31
In/Output
Data Input/Output
Data input/output pin.
DQS0~DQS3
VDD
VSS
VDDQ
VSSQ
NC
In/Output
Supply
Supply
Supply
Supply
NC
Data Input/Output
Strobe
Power Supply
Ground
DQ Power Supply
DQ Ground
No Connection
Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. Data strobe is
used to capture data.
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection.
Rev. A | February 2013
www.issi.com
- dram@issi.com
4
FPGA/CPLD
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