TB62D612FTG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62D612FTG
24-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation
The TB62D612FTG is a constant-current driver designed for LED and LED
display lighting.
The TB62D612FTG incorporates twenty-four channels of seven-bit PWM
dimming controllers and constant-current drivers. Twenty-four constant-current
drivers are divided into three blocks, each consisting of three drivers, and the
output current of each can be independently adjusted by the relevant external
resistor.
The TB62D612FTG is controlled using the SDA and SCLK input signals, and
capable of high-speed data transfers.
The TB62D612FTG can be set address with ID terminal. (Up to 64 address)
High-speed processing is capable by applying Bi-CMOS process.
The TB62D612FTG operates with a supply voltage of 3.3 V or 5 V.
P-WQFN36-0606-0.50-001
Weight: 0.083 g ( typ.)
1． Features
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Power supply voltages: V
CC
= 3.3 V/5 V
Output drive capability and output count: 80 mA (max)× 24 channels
Constant-current output range: 5 to 40 mA
Voltage applied to constant-current output terminals: 0.4 V(min) (I
OUT
= 5 to 40 mA)
Designed for common-anode LEDs
The input interface is controlled by the SDA and SCLK signal lines
Thermal shutdown (TSD)
Logical Input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input)
Maximum output voltage: 28 V
Incorporating PWM control circuitry: Provides seven-bit PWM control.
Driver identification: Up to 64 drivers can be controlled individually.
Operating temperature range: T
opr
=
−40
to 85
°
C
Package: P-WQFN36-0606-0.50-001
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Constant-current accuracy
Output Voltage
0.4 V
Current Accuracy
Between Channels
±3.0%
Current Accuracy
Between ICs
±6.0%
Output Current
15 mA
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TB62D612FTG
2．Pin Assignment
(top view)
RESET
28
19
Rext-G
20
Rext-B
27
SCLK
21
GND
26
SDA
25
Vcc
24
ID2
23
ID1
22
ID0
18
17
16
Rext-R
/OUTB7
/OUTG7
/OUTR7
/OUTB6
/OUTG6
/OUTR6
/OUTB5
/OUTG5
/OUTR0
29
/OUTG0
30
/OUTB0
31
/OUTR1
32
/OUTG1
33
/OUTB1
34
TOP VIEW
15
14
13
12
11
10
/OUTR2
35
/OUTG2
36
5
/OUTR4
6
8
/OUTR3
/OUTG3
/OUTB2
/OUTB3
3．Block Diagram
ID0 ID1 ID2
Vcc
Rext-R
/OUTR5
9
1
2
3
4
/OUTG4
7
/OUTB4
PGND
RESET
SDA
SCLK
Logic
Processing
Adress
Configration
PWM(7bit)
Constant-
Current Driver
/OUTR0
Data
Buffer
PWM(7bit)
PWM(7bit)
Constant-
Current Driver
Constant-
Current Driver
/OUTR7
/OUTG0
GND
CLK
Generation
PWM(7bit)
PWM(7bit)
Constant-
Current Driver
Constant-
Current Driver
/OUTG7
/OUTB0
TSD
PWM(7bit)
Constant-
Current Driver
/OUTB7
Rext-G
Rext-B
PGND
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2012-07-23
TB62D612FTG
4．Terminal Description
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
/OUTB2
/OUTR3
/OUTG3
/OUTB3
PGND
/OUTR4
/OUTG4
/OUTB4
/OUTR5
/OUTG5
/OUTB5
/OUTR6
/OUTG6
/OUTB6
/OUTR7
/OUTG7
/OUTB7
Rext-R
Rext-G
Rext-B
GND
ID0
ID1
ID2
Vcc
SDA
SCLK
RESET
/OUTR0
/OUTG0
/OUTB0
/OUTR1
/OUTG1
/OUTB1
/OUTR2
/OUTG2
Function
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Power Ground pin
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
External resistor pin for output current configuration (/OUTR0 to /OUTR7)
External resistor pin for output current configuration (/OUTG0 to /OUTG7)
External resistor pin for output current configuration (/OUTB0 to /OUTB7)
Ground pin
ID configuration pin (Note 1)
ID configuration pin (Note 1)
ID configuration pin (Note 1)
Power supply terminal
Serial data input terminal
Serial clock input terminal
Reset signal input. (Setting this pin High resets internal data.) (Note 1)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Constant-current output terminal (Open-collector type)
Note 1: After the reset is released, it should be ensured that IDs (slave addresses) are properly configured.
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TB62D612FTG
5．Equivalent Circuits for Inputs and Outputs
SDA and SCLK Terminals
Vcc
RESET Terminals
Vcc
SDA
SCLK
RESET
GND
GND
Constant-Current Output Terminals
ID0, ID1, and ID2 Terminals
Vcc
/OUTR0 to /OUTR7
/OUTG0 to /OUTG7
/OUTB0 to /OUTB7
PGND
ID0
ID1
ID2
↓
GND
Comparison
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TB62D612FTG
6．Programming the TB62D612FTG
The TB62D612FTG can be programmed by the SDA and SCLK signals.
The TB62D612FTG should be programmed using one of the following formats: (1) Serial Packet Format in Normal Programming
Mode or (3) Serial Packet Format in Special Mode.
(1) Serial Packet Format in Normal programming Mode
【Typical】
Start Command
[11111111]
Slave address
8 bits
Sub-address
(Channel select)
8 bits
Data byte
(PWM configuration)
8 bits
Period Command
[10000001]
・Normal
programming Mode should be set as the following flow.
“Start Command”
“Slave address”
“Sub-address”
“Data byte”
“Period Command”
As for example of data input, refer to Page8.
・Input
data from SDA signal is written to the shift register at the rising edge of SCLK every 8 bit.
This data is transferred at the falling edge of the eighth CLK. So, at the eighth CLK, data should be inputted to the falling edge.
Block diagram of data setting part
Data is transferred at
the falling edge of the
eighth SCLK.
Data
Byte
8ビット
8 bit
counter
カウンタ
ＯＵＴ
R0
8bit
ＯＵＴ
G0
8bit
ＯＵＴ
B0
8bit
ＯＵＴ
R1
8bit
Terminal command
終了コマンド
ＯＵＴ
B6
8bit
ＯＵＴ
R7
8bit
ＯＵＴ
G7
8bit
ＯＵＴ
B7
8bit
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
R0
R0
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
G0
G0
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
B0
B0
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
R1
R1
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
B6
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
R7
R7
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
G7
G7
8bit
Data
ﾃﾞ½ﾀﾊﾞ½ﾄ
Byte
B7
B7
8bit
8bit
8bit
8bit
サブアドレス
Sub Address
8bit
8bit
8bit
8bit
8bit
Slave Address
スレーブアドレス
8bit
SDA
8ビットシフトレジスタ
8bit shift-resister
Shift-register
SCLK
Data is written to the shift register at the
rising edge of the SCLK.
In case of period command
Data is transferred at
the falling edge of the
eighth SCLK.
SDA
SCLK
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2012-07-23
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