AN352
L
OW
-C
OS T
, H
I G H
-S
PEED
I 2 C I
S O L A T IO N
1. Introduction
Many articles have been published using opto-couplers
for I2C isolation (See “5. References” on page 3). These
circuits are somewhat complex, sensitive to bus
capacitance, and limited in speed. They are also not
compatible with high-speed digital isolators having
standard CMOS input levels.
This application note shows how to convert a standard
Si8442 high-speed digital isolator to a bidirectional I2C
isolator. In addition to being compatible with digital
isolators, the circuit is simpler than previously published
solutions, completely insensitive to bus capacitance,
and can easily support the standard 400 kHz maximum
I2C bus rate.
Side A
Driver
Isolator
B
Isolator
A
WI TH
D
IGITAL
I
SOLATORS
Side B
Driver
2. Difficulty of Making a Bidirectional
Circuit
Standard I2C SDA and SCL signals are driven by open
drain drivers. In all cases, SDA can be driven by any
device on the bus so that the SDA bus wire
communicates information from the I2C master to the
slaves and from the slaves to the master. That is, the
data transfer is bidirectional. In some cases, the SCL
only has a driver for the I2C master. However, in many
cases, such as multiple I2C masters or if the slave
needs to stretch SCL by holding it low while it retrieves
data, the SCL line must also be bidirectional.
For the wires that need to be bidirectional, if digital
isolators are inserted as in Figure 1, there are several
problems:
The isolators must be open-drain.
There is a latch-up condition that can occur. If, for
example, the side A driver pulls low, isolator A pulls
low on side B. This causes isolator B to pull low on
side A, and the circuit latches with both isolators
pulling low.
Figure 1.
The open drain problem is easily solved by putting a
Schottky diode in series with the isolator output.
However, the latch up problem is much more difficult to
solve.
Previous attempts to solve this problem have used
diodes inherent to the opto-coupler input and additional
circuitry to avoid the latch-up condition (See “5.
References” on page 3). Some of these approaches are
sensitive to bus capacitance. They tend to be slow due
to the slow response of the opto-couplers. Finally, when
higher speed digital isolators with standard CMOS input
levels are used, the circuit tricks using the diode input of
the opto-couplers no longer apply.
3. Circuit Using Digital Isolators
The full circuit using a Silicon Laboratories, Inc. Si8442
high-speed isolator is shown in Figure 2. The circuit
assumes 1 kΩ pull-up resistors on the SCL and SDA
lines. It can be easily adjusted for other bus pull-up
resistors. This circuit has been tested with Silicon
Laboratories, Inc. C8051Fxxx series MCUs at a bus
speed of approximately 300 kHz including bus
transactions that require SCL clock stretching.
Rev. 1.0 8/08
Copyright © 2008 by Silicon Laboratories
AN352
AN352
+3V3LV
+3V3
C1
4.7 µF
C2
0.1 µF
C3
0.1 µF
C4
0.1 µF
R4
1.24 k
R5
4.99 k
Q1
R7
1.24 k
D50B
BAS40-07
R8
4.99 k
Q2
MMBT3904
D50A
MMBT3904
NonIsolated Circuits
U50
16
VDD1
1
VDD2
BAS40-07
R3
316
14
D2A
BAS40-07
R6
316
3 A1
4
SDA1
5
D1A
BAS40-07
6
D1B
BAS40-07
+3V3LV
7
A4
EN1
GND1
GND1
GND2
GND2
B1
SCL2
R1
36.5
R2
36.5
SDA2
A2
ISOLATION
A3
B2
B3
13
D2B
12
BAS40-07
SCL1
B4
EN2
11
+3V3
10
Isolated Circuits
Figure 2. Full Circuit
Diodes D1A,B and D2A,B convert the push-pull output
of the Si8442 to open drain.
The latchup problem described above is solved by
using a comparator to sense whether the non-isolated
side (side A) is causing the low on the isolated side
(side B). Transistors Q1 and Q2 act as the comparators.
If the low on side B is caused by low on side A, Q1 or
Q2 will not turn on due the drop across diodes D2A,B
and R1 or R2 and the low is not propagated back to side
A breaking the latch condition. If the low on side B is
caused by the open drain driver on side B, Q1 and Q2
do turn on, and the low is propagated.
Note that the comparator circuit only needs to be used
on one side and can be used on either side A or side B.
The voltage levels on Side A are completely compatible
with I2C requirements and there is no special
consideration for the side without the comparator circuit.
For side B, with the comparator circuit, the output of the
isolator should not turn on the comparator, but the open
drain driver must turn on the comparator.
The threshold of the comparators is set by the voltage
dividers, R3/R4 and R6/R7. Diodes D3A, B provide
temperature compensation to match diodes D2A,B.
With the component values shown, the comparator
threshold is approximately 0.28 V. The schottky clamp
pulls down to approximately 0.5 V, and the open drain
driver pulls to typically 0.1 V; so, the comparator
threshold is well centered between these values.
If the bus pull-up resistors are not 1 kΩ , the VDD
voltage is not 3.3 V, or if the driver on the side with the
comparator cannot pull below 0.2 V, the circuit will need
to be adjusted. The pull down from the isolator (as
determined by diode D2 and R1or R2) must be adjusted
to be compatible with the logic low of the devices
connected to the bus on side B. The comparator
threshold is set by D3 (to track D2) and the voltage
divider R3/R4 or R6/R7. The comparator threshold is
adjusted to center between the pull down of the isolator
circuit and the pull down of the other I2C circuits on the
I2C bus on side B.
2
15
Si8442
8
2
9
Rev. 1.0
AN352
4. Circuit Performance
The propagation delay from side A (non-isolated side) to
side B (isolated side) introduced by the isolator circuit is
negligible (<50 nsec) for both rising and falling edges.
This is due to the fact that, in this direction, the
comparator is not in the path and introduces no delay.
Figure 3 shows the propagation delay from side B
(isolated side) to side A (non-isolated side).
For the falling edge, the delay is approximately 50 nsec
as the transistor switches on. For the rising edge, there
is a delay of approximately 250 nsec as the transistor
switches off. Also, note that, in this case, the final rise of
the input waveform is delayed so that the skew as the
waveforms cross a typical 1 V CMOS logic threshold is
quite small.
The added delay introduced by this circuit is compatible
with I2C or SMBus operation at speeds up to 400 kHz.
Figure 3. Propagation Delay A (Non Isolated Side ) to B
5. References
1. Blozis, Steve, "Opto-electrical isolation of the I2C-
Bus," Embedded Systems Design, Oct 14, 2004.
2. Jerry Steele, "Temperature sensor uses I2C
isolator", Electronic Design News, June 6, 1996
3. Michele Costantino , "I2C interface has galvanic
isolation, wired-OR capability, improved noise
margin" Electronic Design News Europe, August
2007.
Rev. 1.0
3
AN352
C
ONTACT
I
NFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: PowerProducts@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc.
4
Rev. 1.0
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
