Si53315
1 : 1 0 L
O W
J
I TT E R
U
N I V E R S A L
B
U F F E R
/L
E V E L
T
R A N S L A T O R W IT H
2 : 1 I
N P U T
M
U X A N D
I
N D I V I D U A L
O E ( < 1 . 2 5 G H
Z
)
Features
10 differential or 20 LVCMOS outputs
Ultra-low additive jitter: 100 fs rms
Wide frequency range:
1 MHz to 1.25 GHz
Any-format input with pin selectable
output formats: LVPECL, Low Power
LVPECL, LVDS, CML, HCSL,
LVCMOS
2:1 mux with hot-swappable inputs
Asynchronous output enable
Individual output enable
Low output-output skew: <50 ps
Low propagation delay variation:
<400 ps
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
Excellent power supply noise
rejection (PSRR)
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 25.
Applications
V
DDOA
Q3
Q4
Q4
Description
The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53315 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53315 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53315 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Q6
Q6
V
DDOB
36
35
34
CLK_SEL
39
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
OE2
SFOUT[0]
OE
1
Q2
Q2
GND
Q1
Q1
Q0
Q0
OE0
1
2
3
4
5
6
7
8
9
10
11
Pin Assignments
Si53315
Q5
Q5
38
37
Q3
43
13
12
15
16
17
19
20
14
18
21
V
DD
OE3
CLK0
OE4
V
REF
OE5
CLK1
CLK1
OE
6
Patents pending
Functional Block Diagram
Vref
Generator
Power
Supply
Filtering
V
REF
V
DDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
CLK0
CLK0
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
V
DDOB
OE[5:9]
CLK1
CLK1
Switching
Logic
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
CLK_SEL
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
CLK0
GND
22
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
44
42
41
40
33
32
31
30
OE7
SFOUT[1]
OE8
Q7
Q7
NC
Q8
Q8
Q9
Q9
OE9
GND
PAD
29
28
27
26
25
24
23
Si53315
Si53315
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5. Power Supply (V
DD
and V
DDOX
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.9. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1. Si53315 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
Preliminary Rev. 0.4
Si53315
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML, HCSL, LVCMOS
LVPECL, low power LVPECL,
LVDS, CML, HCSL, LVCMOS
Output Buffer Supply
Voltage*
V
DDO
LVDS, CML, HCSL, LVCMOS
LVPECL, low power LVPECL,
LVDS, CML, HCSL, LVCMOS
Test Condition
Min
–40
1.71
2.38
2.97
1.71
2.38
2.97
Typ
—
1.8
2.5
3.3
—
—
—
Max
85
1.89
2.63
3.63
1.89
2.63
3.63
Unit
°C
V
V
V
V
V
V
*Note:
Core supply
V
DD
and output buffer supplies V
DDO
are independent.
Table 2. Input Clock Specifications
(V
DD
= 1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
= –40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Input Swing
(single-ended, peak-to-
peak)
Input Voltage High
Input Voltage Low
Input Capacitance
Symbol
V
CM
V
IN
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.1
Typ
—
—
Max
—
1.1
Unit
V
V
V
IH
V
IL
C
IN
V
DD
x
0.7
—
—
—
—
5
—
V
DD
x
0.3
—
V
V
pF
Preliminary Rev. 0.4
3
Si53315
Table 3. DC Common Characteristics
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz
Symbol
I
DD
I
DDOX
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
CMOS (1.8 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (2.5 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, C
L
= 5 pF, 200 MHz
Leakage Current
I
L
Input leakage at all inputs except
CLKIN, V
IN
= 0 V
Input leakage at CLKIN
V
IN
= 0 V
Voltage Reference
Input High Voltage
Input Mid Voltage
Input Low Voltage
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
REF
V
IH
V
IM
V
IL
R
DOWN
R
UP
V
REF
pin
SFOUTX, DIVX
3-level input pins
SFOUTX, DIVX
3-level input pins
SFOUTX, DIVXpin
3-level input pins
CLK_SEL, DIVA, DIVB, SFOUTA[1],
SFOUTB[1]
SFOUTA[1], SFOUTB[1], DIVA,
DIVB, OEX, OEX
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
0.85 x
VDD
0.45 x
VDD
—
—
—
Typ
TBD
35
30
20
30
35
5
8
15
—
—
VDD/2
—
0.5 x
VDD
—
25
25
Max
100
—
—
—
—
—
—
—
—
TBD
TBD
—
—
0.55 x
VDD
0.15 x
VDD
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
kΩ
kΩ
4
Preliminary Rev. 0.4
Si53315
Table 4. DC Characteristics—LVPECL and Low Power LVPECL
(V
DD
= 2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Parameter
Output Voltage High
Output Voltage Low
Output DC Common
Mode Voltage
Single-Ended
Output Swing
Symbol
V
OH
V
OL
V
COM
V
SE
Terminate unused outputs to
R
L
= 50
Ω
to V
DDOX
– 2 V
Test Condition
R
L
= 50
Ω
to V
DDOX
– 2 V
R
L
= 50
Ω
to V
DDOX
– 2 V
Min
V
DDOX
–
1.145
V
DDOX
–
1.945
V
DDOX
–
1.895
0.25
Typ
—
—
—
0.60
Max
V
DDOX
–
0.895
V
DDOX
–
1.695
V
DDOX
–
1.425
0.85
Unit
V
V
V
V
Table 5. DC Characteristics—CML
Parameter
Single-Ended Output
Swing
Symbol
V
SE
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Test Condition
Terminated as shown in Figure 6
(CML termination).
Min
300
Typ
400
Max
500
Unit
mV
Table 6. DC Characteristics—LVDS
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(V
DDO
= 2.5 V or
3.3 V)
Output Common
Mode Voltage
(V
DDO
= 1.8 V)
Symbol
V
SE
V
COM1
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Test Condition
R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 2.38 to 2.63 V, 2.97 to
3.63 V, R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 1.71 to 1.89 V,
R
L
= 100
Ω
across Q
N
and Q
N
Min
247
1.10
Typ
—
1.25
Max
454
1.35
Unit
mV
V
V
COM2
0.85
0.97
1.10
V
Preliminary Rev. 0.4
5
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