CAT884
Quad Voltage Supervisor
Description
The CAT884 is a four−channel power supply supervisory circuit
with high accuracy reset thresholds and very low power consumption.
The device features an active−low open−drain output with manual
reset to perform basic system reset and voltage monitoring functions
for a wide range of electronic products.
CAT884 monitors four system voltages maintaining its reset output
active until all the power supply voltages exceed the specified
threshold values. The four threshold voltages are user controlled and
can be set for system specific requirements over a range of 0.635 V to
5.5 V using external resistor dividers.
The CAT884 lowers system costs and saves board space by
integrating four channels into a single, small SOIC 8−lead package
and operates over the industrial temperature range of
−40°C
to +85°C.
Features
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SOIC−8
V SUFFIX
CASE 751BD
PIN CONNECTIONS
V
DD
RESET
MR
GND
(Top View)
1
V1
V2
V3
V4
•
•
•
•
•
•
•
Quad Voltage Monitoring
Adjustable Threshold Voltages down to 0.635 V with
±2%
Accuracy
Low Supply Current: 3
mA
(typ)
RESET Valid to V
CC
= 1 V
Immune to Short Supply Transients
Operating Temperature Range:
−40°C
to +85°C
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
Applications
•
Monitoring of Multiple Power Supply Voltages in
mP
Based Systems
S1 S2 S3 S4
V+
Optional
mP
Reset
Manual
Reset
884VYM
V1
V2
V3
V4
V
DD
RESET
MR
GND
884V = Device Code
Y = Production Year (Last Digit)
M = Production Month: 1−9, A, B, C
ORDERING INFORMATION
Device
CAT884RVI−GT3
Package
SOIC−8
(Pb−Free)
Shipping
†
3,000/
Tape & Reel
Figure 1. Typical Application Circuit
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2010
October, 2010
−
Rev. 0
1
Publication Order Number:
CAT884/D
CAT884
30
ms
Filter
0.635 V
+
−
V2
30
ms
Filter
0.635 V
+
−
V3
30
ms
Filter
0.635 V
+
−
V4
30
ms
Filter
0.635 V
+
−
−
+
−
+
MR
−
+
RESET
V1
−
+
POR
V
DD
V+
GND
Figure 2. CAT884 Block Diagram
Table 1. PIN FUNCTION
Pin Number
1
2
3
4
5
6
7
8
Pin Name
VDD
RESET
MR
GND
V4
V3
V2
V1
Chip power supply
Open Drain active LOW reset output
Manual Reset
Ground
Fourth adjustable under−voltage detector input
Third adjustable under−voltage detector input
Second adjustable under−voltage detector input
First adjustable under−voltage detector input
Function
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
V
DD
, V1−V4, MR, RESET to GND
Continuous RESET Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Lead Temperature (soldering, 10 s)
Value
−0.3
to +6.0
20
−40
to +85
−65
to +150
+150
+300
Unit
V
mA
°C
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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CAT884
Table 3. ELECTRICAL CHARACTERISTICS
(V
DD
= 1.0 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise noted. Typical values are at V
DD
= 3.0 V to 3.3 V, T
A
= +25°C. (Note 1))
Symbol
V
DD
I
DD
V
POR_
Parameter
Operating Voltage
Supply Current
V
DD
Input Voltage Threshold
V
DD
= 5 V
V
DD
low
³
High
V
DD
High
³
Low
RESET OUTPUT
V
OL
RIN
TCV
TH
t
RPD
RESET Output Low
V
CC
≥
5 V, I
SINK
= 2.5 mA
V
CC
< 3.3 V, I
SINK
= 1.5 mA
Internal Pull−Up Resistor
Reset Threshold Temperature
Coefficient
Delay; V
IN
to Reset
V
IN
falling at 10 mV/ms from V
TH
to
(V
TH
– 50 mV)
1
0.05
0.05
20
60
1.5
0.4
0.4
kW
ppm/°C
ms
V
Test Conditions
Min
1.5
3
2.6
2.4
Typ
Max
5.5
9
Units
V
mA
V
VOLTAGE THRESHOLD
V
TH
V
HYST
V
TH_VAR
t
FIL
t
RD
Adjustable Threshold
Reset Threshold Hysteresis
Variance of V
TH
voltages
Glitch Filter Delay
Delay; V
MON
to Reset
Monitored voltage decreasing
Monitored voltage increasing compared
to monitored voltage decreasing
V
TH
(max)
−
V
TH
(min) (Note 4)
V
MON
glitch to RST low Filter
V
MON
falling at 10 mV/ms from V
TH
to
(V
TH
– 50 mV)
1
0.619
0.635
10
1.8
30
2
0.651
V
mV
mV
ms
ms
MANUAL RESET INPUT
VTHL
VTHH
T
PW
IPU
t
MD
t
MR
1.
2.
3.
4.
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Pull−Up Current
MR to Deassert Reset output
delay
MR to Assert Reset output
delay
VDD
−
0.6
20
10
40
30
0.8
V
V
ns
mA
ns
ns
100% production tested at T
A
= +25°C. Limits over temperature guaranteed by design.
The devices are powered from V
DD
.
The RESET output is guaranteed to be in the correct state for V
DD
down to 1 V.
Not tested in production but guaranteed by design.
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CAT884
TYPICAL CHARACTERISTICS
(V
DD
= 3.0 V, T
A
= +25°C, unless specified otherwise.)
3.15
3.10
3.05
3.00
2.95
2.90
T = 25°C
2480
2440
VTH (mV)
6.5
I
DD
(mA)
2400
2360
2.5
3.5
4.5
V
DD
(V)
5.5
2320
−40
25
TEMPERATURE (°C)
90
Figure 3. I
DD
Input Current vs. Temperature
640
638
636
634
632
630
−40
VTH DN
T_FIL (mS)
32
Figure 4. V
DD
Input Voltage Threshold
(High to Low)
T = 25°C
31
VTH (mV)
30
29
25
TEMPERATURE (°C)
90
28
1.5
2.5
3.5
V
DD
(V)
4.5
5.5
6.5
Figure 5. Monitored Voltages Decreasing
Figure 6. Glitch Filter Delay for Voltage
Monitors
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CAT884
Detailed Description
The CAT884 is a space−saving, low−power, quad voltage
microprocessor supervisory circuit designed monitor 4
voltage supplies.
Applications Information
Reset Output
3.3 V
CAT884
V1
V2
V3
V4
V
DD
RESET
mP
RESET
5V
CAT884 provides an active LOW system reset signal via
an open drain output which requires an external pull−up
resistor to an external power supply. This supply can be less
than or greater than V
DD
, but should not exceed 5.5 V. When
the external pull−up voltage is greater than V
DD
reverse
current flow from the external pull−up voltage to V
DD
is
prevented by CAT884’s internal circuitry.
V
DD
is also a monitored voltage in CAT884 with
thresholds set for 2.6 V rising and 2.4 V falling. When any
monitored supply drops below its threshold, the reset output
asserts LOW and remains LOW as long as V
DD
is above
1.0 V.
Figure 7. Interfacing to Different Logic−Supply
Voltage
V
DD
0
V
MON
0
V
POR
1V
V
TH
<t
FIL
>T
PW
MR
0
RST
0
t
MR
t
RPD
t
RD
t
FIL
t
MD
Figure 8. Operational Timing Diagram
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