MMSF7N03Z
Power MOSFET
7 Amps, 30 Volts
N−Channel SO−8
EZFETst are an advanced series of Power MOSFETs which contain
monolithic back−to−back zener diodes. These zener diodes provide
protection against ESD and unexpected transients. These miniature
surface mount MOSFETs feature ultra low R
DS(on)
and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain−to−source diode has a
very low reverse recovery time. EZFET devices are designed for use in
low voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives.
•
Zener Protected Gates Provide Electrostatic Discharge Protection
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery
Life
•
Designed to withstand 200V Machine Model and 2000V Human
Body Model
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Mounting Information for SO−8 Package Provided
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7 AMPERES
30 VOLTS
R
DS(on)
= 30 mW
N−Channel
D
G
S
MARKING
DIAGRAM
8
1
7N03Z
L
Y
WW
SO−8
CASE 751
STYLE 12
7N03Z
LYWW
= Device Code
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
Source
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
ORDERING INFORMATION
Device
MMSF7N03ZR2
Package
SO−8
Shipping
2500 Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 2
1
Publication Order Number:
MMSF7N03Z/D
MMSF7N03Z
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
A
= 25°C (Note 1)
−
Continuous @ T
A
= 70°C (Note 1)
−
Pulsed Drain Current (Note 3)
Total Power Dissipation @ T
A
= 25°C (Note 1)
Linear Derating Factor (Note 1)
Total Power Dissipation @ T
A
= 25°C (Note 2)
Linear Derating Factor (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy
−
Starting T
J
= 25°C
(V
DD
= 30 Vdc, V
GS
= 5.0 Vdc, Peak I
L
= 15 Apk, L = 4.0 mH, R
G
= 25
Ω)
Thermal Resistance
−
Junction to Ambient (Note 1)
−
Junction to Ambient (Note 2)
1. When mounted on 1″ square FR−4 or G−10 board (V
GS
= 10 V, @ 10 Seconds)
2. When mounted on 1″ square FR−4 or G−10 board (V
GS
= 10 V, @ Steady State)
3. Repetitive rating; pulse width limited by maximum junction temperature.
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
Value
30
30
±
15
7.5
5.6
60
2.5
20
1.6
12
−
55 to 150
450
50
80
°C/W
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
mW/°C
Watts
mW/°C
°C
mJ
I
DM
P
D
P
D
T
J
, T
stg
E
AS
R
θJA
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2
MMSF7N03Z
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
15 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 4)
Gate Threshold Voltage
(Cpk
≥
2.0)
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 7.5 Adc)
(V
GS
= 4.5 Vdc, I
D
= 3.8 Adc)
(Cpk
≥
2.0)
(Notes 4 & 6)
V
GS(th)
Vdc
1.0
−
−
−
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2.0
5.5
22
30
9.5
750
340
45
40
90
470
170
120
350
430
140
34
3.5
9.5
6.5
3.0
−
30
40
−
1500
680
90
80
180
940
340
240
700
860
280
48
−
−
−
Vdc
−
−
−
−
−
−
0.83
0.67
110
22
90
0.17
1.6
−
−
−
−
−
μC
ns
nC
ns
ns
Mhos
pF
mV/°C
mΩ
(Cpk
≥
2.0)
(Notes 4 & 6)
V
(BR)DSS
Vdc
30
−
−
−
−
−
35
0.03
0.15
1.3
−
−
2.0
10
5.0
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
μAdc
(Notes 4 & 6)
R
DS(on)
Forward Transconductance (V
DS
= 3.0 Vdc, I
D
= 3.8 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(Note 4)
g
FS
C
iss
C
oss
C
rss
t
d(on)
(V
DS
= 24 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
(V
DS
= 15 Vdc, I
D
= 5.0 Adc,
V
GS
= 10 Vdc, R
G
= 6
Ω)
(Note 4)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
(V
DD
= 15 Vdc, I
D
= 5.0 Adc,
V
GS
= 4.5 Vdc, R
G
= 6
Ω)
(Note 4)
(V
DS
= 24 Vdc, I
D
= 5.0 Adc,
V
GS
= 10 Vdc) (Note 4)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 4)
(I
S
= 7.5 Adc, V
GS
= 0 Vdc) (Note 4)
(I
S
= 7.5 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
(I
S
= 7.5 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs) (Note 4)
Reverse Recovery Storage Charge
4. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
5. Switching characteristics are independent of operating junction temperatures.
Max limit
−
Typ
6. Reflects typical values.
C
pk
=
3 x SIGMA
V
SD
Reverse Recovery Time
t
rr
t
a
t
b
Q
RR
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MMSF7N03Z
TYPICAL ELECTRICAL CHARACTERISTICS
10
I D , DRAIN CURRENT (AMPS)
10
3.5 V
8
V
GS
= 10 V
4.5 V
3.8 V
I D , DRAIN CURRENT (AMPS)
8
T
J
= 25°C
V
DS
≥
10 V
6
3.3 V
6
4
3.1 V
2
2.7 V
0
0
0.4
0.8
1.2
1.6
2
4
100°C
2
25°C
T
J
= −55°C
0
1.8
2.2
2.6
3
3.4
3.8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.1
I
D
= 2.5 A
T
J
= 25°C
0.08
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.05
T
J
= 25°C
0.04
V
GS
= 4.5
10 V
0.02
0.06
0.03
0.04
0.02
0.01
0
0
4
6
8
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
2
10
0
0
2
4
6
8
10
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
V
GS
= 10 V
I
D
= 2.5 A
I DSS , LEAKAGE (nA)
1.5
1000
V
GS
= 0 V
100
T
J
= 125°C
1.0
100°C
10
0.5
0
−50
−25
0
25
50
75
100
125
150
1
0
5
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation
with Temperature
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4
Figure 6. Drain−to−Source Leakage Current
versus Voltage
MMSF7N03Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
2500
2000
C, CAPACITANCE (pF)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
V
GS
= 0 V
1500
C
iss
1000
C
oss
C
rss
0
0
6
12
18
24
30
500
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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