Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
Symbol
R
θJC
R
θCS
R
θJA
T
L
Max
2.2
2.2 (typ)
60
260
Unit
°C/W
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(V
D
= Rated V
DRM
, V
RRM
; Gate Open)
T
J
= 25°
T
J
= 125°C
I
DRM
,
I
RRM
−
−
−
−
10
2.0
μA
mA
ON CHARACTERISTICS
Peak On-State Voltage (Note 1)
(I
TM
=
"11.3
A Peak)
Gate Trigger Current (Continuous dc) (V
D
= 12 Vdc, R
L
= 100
Ω)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
Gate Trigger Voltage (Continuous dc)
(Main Terminal Voltage = 12 Vdc, R
L
= 100 Ohms)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
Gate Non−Trigger Voltage (Continuous dc)
(Main Terminal Voltage = 12 V, R
L
= 100
Ω,
T
J
= +125°C)
All Four Quadrants
Holding Current
(V
D
= 12 Vdc, Gate Open, Initiating Current =
"200
mA)
V
TM
I
GT
−
1.7
2.0
Volts
mA
−
−
−
−
−
−
−
−
50
50
50
75
Volts
−
−
−
−
V
GD
0.2
0.9
0.9
1.1
1.4
−
2.0
2.0
2.0
2.5
−
Volts
V
GT
I
H
−
−
50
mA
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Commutating Off−State Voltage
(V
D
= Rated V
DRM
, I
TM
= 11.3 A, Commutating
di/dt = 4.1 A/ms, Gate Unenergized, T
C
= 80°C)
Critical Rate of Rise of Off−State Voltage
(V
D
= Rated V
DRM
, Exponential Voltage Rise, Gate Open,
T
J
= 125°C)
1. Pulse Test: Pulse Width
≤
2.0 ms, Duty Cycle
≤
2%.
dv/dt
(c)
−
5.0
−
V/μs
dv/dt
−
100
−
V/μs
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2
MAC218A6FP, MAC218A8FP MAC218A10FP
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Quadrant 1
MainTerminal 2 +
Symbol
V
DRM
I
DRM
V
RRM
I
RRM
V
TM
I
H
Parameter
Peak Repetitive Forward Off State Voltage
Peak Forward Blocking Current
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
Maximum On State Voltage
Holding Current
Quadrant 3
MainTerminal 2
−
I
H
V
TM
I
RRM
at V
RRM
on state
I
H
V
TM
off state
+ Voltage
I
DRM
at V
DRM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
(+) MT2
Quadrant II
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
Quadrant I
I
GT
−
(−) MT2
(−) MT2
+ I
GT
Quadrant III
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
Quadrant IV
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
MAC218A6FP, MAC218A8FP MAC218A10FP
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (
°
C)
PD(AV), AVERAGE POWER DISSIPATION (WATTS)
125
115
105
95
85
75
10
8
6
4
2
0
0
1
3
4
5
6
I
T(RMS)
, RMS ON−STATE CURRENT (AMPS)
2
7
8
0
1
3
4
5
6
I
T(RMS)
, RMS ON−STATE CURRENT (AMPS)
2
7
8
Figure 1. Current Derating
VGT, NORMALIZED GATE TRIGGER VOLTAGE (VOLTS)
Figure 2. Power Dissipation
I GT, NORMALIZED GATE TRIGGER CURRENT (mA)
5
MAIN TERMINAL VOLTAGE = 12 V
1.8
1.6
1.4
1.2
1
0.8
0.6
QUADRANTS
1
2
3
MAIN TERMINAL VOLTAGE = 12 V
3
2
QUADRANT 4
1
0.7
QUADRANT
1
2
3
4
0
20
40
60
80
100
T
J
, JUNCTION TEMPERATURE (°C)
120
140
0.5
−60
−40
−20
0.4
−60
−40
−20
0
20
40
60
80
100
T
J
, JUNCTION TEMPERATURE (°C)
120
140
Figure 3. Normalized Gate Trigger Current
Figure 4. Normalized Gate Trigger Voltage
I H , NORMALIZED HOLDING CURRENT (mA)
2
GATE OPEN
MAIN TERMINAL #1
POSITIVE
1
0.7
0.5
MAIN TERMINAL #2
POSITIVE
0.3
0.2
−60
−40
−20
0
20
40
60
80
100
120
140
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. Normalized Holding Current
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4
MAC218A6FP, MAC218A8FP MAC218A10FP
PACKAGE DIMENSIONS
TO−220 FULLPACK THYRISTOR
CASE 221C−02
ISSUE D
−B−
P
−T−
F
N
E
C
S
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. LEAD DIMENSIONS UNCONTROLLED WITHIN
DIMENSION Z.
DIM
A
B
C
D
E
F
G
H
J
K
L
N
P
Q
R
S
Z
INCHES
MIN
MAX
0.680
0.700
0.388
0.408
0.175
0.195
0.025
0.040
0.340
0.355
0.140
0.150
0.100 BSC
0.110
0.155
0.018
0.028
0.500
0.550
0.045
0.070
0.049
−−−
0.270
0.290
0.480
0.500
0.090
0.120
0.105
0.115
0.070
0.090
MILLIMETERS
MIN
MAX
17.28
17.78
9.86
10.36
4.45
4.95
0.64
1.01
8.64
9.01
3.56
3.81
2.54 BSC
2.80
3.93
0.46
0.71
12.70
13.97
1.15
1.77
1.25
−−−
6.86
7.36
12.20
12.70
2.29
3.04
2.67
2.92
1.78
2.28
H
−Y−
Q
1 2 3
A
K
Z
L
G
D
3 PL
J
R
0.25 (0.010)
M
B
M
Y
STYLE 3:
PIN 1. MT 1
2. MT 2
3. GATE
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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