74LVX08 — Low Voltage Quad 2-Input AND Gate
June 2014
74LVX08
Low Voltage Quad 2-Input AND Gate
Features
• Input Voltage Level Translation from 5 V to 3 V
• Ideal for Low-power / Low-Noise 3.3 V Applications
• Guaranteed Simultaneous Switching Noise Level and
Dynamic threshold Performance
Description
The LVX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7 V allowing the interface of 5 V
systems to 3 V systems.
Ordering Information
Part Number Top Mark Package Packing Method
74LVX08M
74LVX08MX
74LVX08MTCX
LVX08
LVX08
LVX08
SOIC 14L
SOIC 14L
TSSOP 14L
Rail
Tape and Reel
Tape and Reel
Packing Description
14-Lead Small Outline Integrated Circuit, JEDEC
MS-012, 0.150 inch Narrow
14-Lead Small Outline Integrated Circuit, JEDEC
MS-012, 0.150 inch Narrow
14-Lead Thin Shrink Small Outline Package,
JEDEC MO-153, 4.4 mm Wide
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Inputs
Outputs
Description
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
www.fairchildsemi.com
1
74LVX08 — Low Voltage Quad 2-Input AND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
T
STG
P
T
L
Supply Voltage
Parameter
DC Input Diode Current, V
I
= -0.5 V
DC Input Voltage
DC Output Diode Current
DC Output Voltage
DC Output Source or Sink Current
Storage Temperature
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
V
O
= -0.5 V
V
O
= V
CC
+ 0.5 V
Rating
-0.5 V to 7.0 V
-20 mA
-0.5 V to 7.0 V
-20 mA
+20 mA
-0.5 V to V
CC
+ 0.5 V
±25 mA
±50 mA
-65°C to 150°C
180 mW
240°C
I
CC
or I
GND
DC V
CC
or Ground Current
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
Δt
/
ΔV
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
Parameter
Rating
2.0 V to 3.6 V
0 V to 5.5 V
0 V to V
CC
-40°C to 85°C
0 ns/V to 100 ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
www.fairchildsemi.com
2
74LVX08 — Low Voltage Quad 2-Input AND Gate
DC Electrical Characteristics
Symbol
Parameter
V
CC
2.0
V
IH
HIGH Level Input
Voltage
3.0
3.6
2.0
V
IL
LOW Level Input
Voltage
3.0
3.6
2.0
V
OH
HIGH Level Output
Voltage
V
IN
= V
IL
or V
IH
,
I
OH
= -50
μA
V
IN
= V
IL
or V
IH
,
I
OH
= -50
μA
V
IN
= V
IL
or V
IH
,
I
OH
= -4 mA
V
IN
= V
IL
or V
IH
,
I
OL
= -50
μA
V
IN
= V
IL
or V
IH
,
I
OL
= -50
μA
V
IN
= V
IL
or V
IH
,
I
OL
= -4 mA
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±0.1
2.0
2.0
3.0
Conditions
Min.
1.5
2.0
2.4
T
A
= 25°C
Typ.
Max.
T
A
= -40°C to
+85°C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
±1.0
20.0
0.5
0.8
0.8
Unit
Max.
V
V
V
3.0
2.0
V
OL
LOW Level Output
Voltage
V
3.0
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
3.6
3.6
μA
μA
Noise Characteristics
(2)
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
3.3
3.3
3.3
3.3
C
L
(pF)
50
50
50
50
T
A
= 25°C
Typ.
0.3
-0.3
Limit
0.5
-0.5
2.0
0.8
Unit
V
V
V
V
Note:
2. Input t
r
= t
f
= 3 ns
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
www.fairchildsemi.com
3
74LVX08 — Low Voltage Quad 2-Input AND Gate
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
C
L
(pF)
Min.
2.7
t
PLH
, t
PHL
Propagation Delay Time
3.3 ± 0.3
t
OSLH
,
t
OSHL
Output to Output Skew
(3)
2.7
3.3
15
50
15
50
50
T
A
= 25°C
Typ.
6.3
8.8
4.8
7.3
T
A
= -40°C to
+85°C
Max.
11.4
14.9
7.1
10.6
1.5
1.5
Unit
Min.
1.0
1.0
1.0
1.0
Max.
13.5
17.0
8.5
12.0
1.5
1.5
ns
ns
Note:
3. Parameter guaranteed by design t
OSLH
= I t
PLHm
- t
PLHn
I, t
OSHL
= I t
PHLm
- t
PHLn
I.
Capacitance
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(4)
Parameter
Min.
T
A
= 25°C
Typ.
4
18
T
A
= -40°C to
+85°C
Max.
10
Unit
pF
pF
Min.
Max.
10
Note:
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
C
PD
x V
CC
x f
IN
x I
CC
Average operating current can be obtained by the eqation: I
CC(opr.)
=
4 (per Gate)
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
www.fairchildsemi.com
4
74LVX08 — Low Voltage Quad 2-Input AND Gate
Physical Dimensions
SOIC 14L
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
1.70
C B A
PIN ONE
INDICATOR
1
1.27
(0.33)
0.51
0.35
0.25
M
7
1.27
LAND PATTERN RECOMMENDATION
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
0.25
0.19
R0.10
R0.10
8°
0°
0.50
X 45°
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 inch Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M1/M14A.pdf.
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
www.fairchildsemi.com
5
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