MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.1 Product Summary
This LSI user's manual describes MN101LR05D/04D/03D/02D.
The detail of product specification is described mainly about MN101LR05D.
For the difference between each product, See [1.3 Comparison of Product Specification] and [1.4.1 Pin Configu-
ration].
V
DD18
voltage after reset release, oscillation stabilization wait time after reset release and ROM capacity vary
depending on the ROM name of each product. Table: 1.1.1 shows the difference of specifications between the
ROM name.
Table:1.1.1 Product Summary
Product Name
ROM name * V
DD18
voltage after
reset release
XW
XX
XY
XZ
XA
XB
XC
XD
1.8 V
2
8
/(f
SRC
/2)
1.1 V
Oscillation stabiliza-
tion wait time after
reset release
2
11
/(f
SRC
/2)
ROM (ReRAM) capacity
(Program area/Data area)
62 KB / 2 KB
59 KB / 4 KB
53 KB / 8 KB
41 KB / 16 KB
62 KB / 2 KB
59 KB / 4 KB
53 KB / 8 KB
41 KB / 16 KB
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
* ROM name: XA/XB/XC/XD/XW/XX/XY/XZ indicates the product that ReRAM is blank.
When using the debugger or programmer, set "Product name + ROM name"
(e.g.: MN101LR05DXA/XW) in the field "Product type" or "Microcomputer product type".
..
When "ROM name" is set incorrectly, connect error is occurred.
When nothing is set to "ROM name", XA/XW is selected.
(e.g.: MN101LR05D
MN101LR05DXA/XW)
..
Publication date: October 2014
1
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.2 Hardware Features
Features
In this document, the divided clock and the frequency of it are described as follows:
Divided clock:Clock name/n (n: division ratio)
Frequency: f
Clock name
• CPU Core
- AM13L core
- LOAD-STORE architecture (3- or 4-stage Pipeline)
• Machine Cycle and Operating Voltage
- High-Speed mode
100 ns / 10 MHz (Max) (V
DD30
: 1.8 V to 3.6 V)
1.0
s
/ 1 MHz (Max) (V
DD30
: 1.3 V to 3.6 V)
- Low-Speed Mode
25
s
/ 40 kHz (Max) (V
DD30
: 1.1 V to 3.6 V)
• Operating Mode
- NORMAL mode (High-Speed mode)
- SLOW mode
(Low-Speed mode)
- HALT mode
(High-Speed/Low-Speed mode)
- STOP mode
• Embedded Memory
- ROM (ReRAM): 64 KB (Programmable area and Data area vary depending on the ROM name.
For details, see Table:1.1.1.)
- RAM:
4 KB
• ReRAM Specification
- Program voltage (V
DD30
): 1.8 V to 3.6 V
- Program cycles:
1000 times (Program area), 100000 times (Data area)
- Data is rewritable in bytes without data erase.
• Clock Oscillator (4 circuits)
- External Low-Speed Oscillation (SOSCCLK): 32.768 kHz (crystal or ceramic)
- External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic)
- Internal Low-Speed Oscillation (SRCCLK):
40 kHz ± 20 % (V
DD30
: 1.1 V to 3.6 V)
- Internal High-Speed Oscillation (HRCCLK): 10/8 MHz ± 3 % (V
DD30
: 1.8 V to 3.6 V)
1 MHz ± 10 % (V
DD30
: 1.3 V to 3.6 V)
* MN101LR02D does not have external high-speed oscillation (HOSCCLK).
• Internal Operating Clock
- System Clock (SYSCLK): 10 MHz (Max)
SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32.
HCLK: HOSCCLK or HRCCLK
SCLK: SOSCCLK or SRCCLK
* MN101LR02D cannot be selected HOSCCLK.
Publication date: October 2014
2
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
• Interrupt Circuit
MN101LR05D/04D/03D: 31 internal interrupts (except for NMI)
8 external interrupts (IRQ interrupt: 7, KEY interrupt: 1)
MN101LR02D:
29 internal interrupts (except for NMI)
3 external interrupts (IRQ interrupt: 2, KEY interrupt: 1)
• DMA (1 channel)
- Data transfer size:
8 bits/16 bits
- Maximum transfer counts: 1023
- Activation trigger:
external interrupts / internal interrupts / software (setting the DMA start bit)
• Watchdog Timer (WDT)
- Function:
1st watchdog time-out generates NMI, and 2nd consecutive time-out generates a LSI reset.
- Clock Source: WDTCLK (SOSCCLK or SRCCLK)
• Timer Counter: 13 units
- General-purpose 8-bit timer (Timer 0/1/2/3/4/5): 6 units
- General-purpose 16-bit timer (Timer 7/8/9):
3 units
- 8-bit free-run (Timer 6) /Time-base timer:
1 unit each
- RTC time base timer (RTC-TBT):
1 unit
- Real Time Clock (RTC):
1 unit
<Timer 0>
- Function:
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM0IO input
<Timer 1 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 0)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM1IO input
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM2IO input
* MN101LR02D cannot be used simple pulse width measurement.
<Timer 3 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 2)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM3IO input
<Timer 4>
- Function:
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM4IO input
<Timer 5 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 4)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM5IO input
* MN101LR02D cannot be used square wave output, event count and TM5IO.
<Timer 2>
- Function:
Publication date: October 2014
3
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
<Timer 6>
- Function:
One-minute timer can be generated in combination with a time base timer.
- Clock Source: HCLK, HCLK/2
7
, HCLK/2
13
, SYSCLK, SCLK, SCLK/2
7
or SCLK/2
13
<Time Base Timer>
- Function:
An interrupt can be generated at a given set time.
- Clock Source: HCLK or SCLK
- Interrupt generation cycle: 2
N
/f
HCLK
, 2
N
/f
SCLK
(N = 7, 8, 9, 10, 12, 13, 14, 15)
<Timer 7>
- Function:
Square wave output, PWM output (duty/cycle are programmable), one-shot pulse output,
IGBT output, event count, and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM7IO input by 1, 2, 4 or 16.
<Timer 8 >
- Function:
Square wave output, PWM output (duty/cycle are programmable), event count,
and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM8IO input by 1, 2, 4 or 16.
<Timer 9 >
- Function:
Square wave output, PWM output (duty/cycle are programmable), event count,
and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM9IO input by 1, 2, 4 or 16.
* MN101LR03D and MN101LR02D
cannot be used square wave output, PWM output, event count and TM9IO.
<RTC time base timer (RTC-TBT)>
- Function:
Clock generation for the Real Time Clock (RTC)
Frequency correction
(Correction Range: ±488 ppm to ±31220 ppm, Accuracy: approx. 0.48 ppm to 30.52 ppm)
- Clock Source: SOSCCLK or SRCCLK
<Real Time Clock (RTC)>
- Function: Calendar calculation, adjustment of leap year
Periodic interrupt (0.5 s, 1 s, 1 min or 1 hour)
Alarm0 interrupt (date/hour/minute), Alarm1 interrupt (month/day/hour/minute)
• Buzzer Output/Inverted Buzzer Output
- Output frequency: f
HCLK
/2
M
(M = 9, 10, 11, 12, 13, 14), f
SCLK
/2
N
(N = 3, 4)
* MN101LR02D can be used inverted buzzer output only.
• Serial Interface: 4 units
<Serial Interface 0, 1> (Full duplex UART/Clock synchronous serial)
- Function:
Full duplex UART:
Parity check, Detection of overrun error/framing error, Selectable transfer bits of 7 or 8
Clock synchronous serial (SPI compatible):
2,3 or 4-wire communication, MSB/LSB first selectable, multiple bytes transmission is available.
- Clock Source: external clock, dedicated baud rate timer
<Serial Interface 2, 3> (Multi-master IIC/Clock synchronous serial)
- Function:
Multi-master IIC
Clock synchronous serial (SPI compatible):
2,3 or 4-wire communication, MSB/LSB first selectable, multiple bytes transmission is available.
- Clock Source: external clock, dedicated baud rate timer
Publication date: October 2014
4
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
* MN101LR03D
Serial Interface 3: Clock synchronous serial can be used in 2-wire communication only,
and is not compatible with SPI. (Chip select pin is not assigned.)
* MN101LR02D
Serial Interface 1: Not implemented
Serial Interface 3: Clock synchronous serial can be used in 2 or 3-wire communication,
and is not compatible with SPI. (Chip select pin is not assigned.)
• A/D Converter (ADC): 1 unit
- Resolution: 12 bits
- Analog signal input channel
MN101LR05D: 8 channels
MN101LR04D: 6 channels
MN101LR03D: 4 channels
MN101LR02D: 3 channels
• I/O ports
MN101LR05D: 69 pins (selectable N-channel transistor drive strength: 55 pins)
MN101LR04D: 53 pins (selectable N-channel transistor drive strength: 41 pins)
MN101LR03D: 37 pins (selectable N-channel transistor drive strength: 27 pins)
MN101LR02D: 22 pins (selectable N-channel transistor drive strength: 19 pins)
• Clock Output
- HCLK, SCLK, SYSCLK or RTCCLK can be output.
• Automatic Reset Circuit
• Low-voltage Detection Circuit (LVI)
• LCD Driver
<MN101LR05D>
43 segment outputs, 4 common outputs (39 segment outputs, 8 common outputs)
Display mode: Static, 1/2 to 1/8 duty
Bias: 1/2, 1/3 (Built-in boost/ External resistor divider)
<MN101LR04D>
31 segment outputs, 4 common outputs
Display mode: Static, 1/2 to 1/4 duty
<MN101LR03D>
21 segment outputs, 4 common outputs
Display mode: Static, 1/2 to 1/4 duty
* MN101LR02D does not have LCD driver function.
Publication date: October 2014
5
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