MN101E77 Series
(Tentative)
8-bit Single-chip Microcontroller
Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate
multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone,
home automation, pager, air conditioner, PPC, remote controller, fax machine, music instrument and other applications.
This LSI brings to embedded microcomputer and applications
flexible,
optimized hardware configurations and a simple
efficient instruction set. MN101EF77G has an internal 128 KB of ROM 2 KB of RAM. Peripheral functions include 6 external
interrupts, 13 internal interrupts including NMI, 7 timer counters, 1 type of serial interfaces, A/D converter and 2 types of
watchdog timer. The system configuration is suitable for system control microcontroller such as camera, timer selector for VCR,
CD player, or MD.
With 4 oscillation systems (high-speed (internal frequency: 16 MHz), high-speed (crystal/ceramic frequency: max. 10 MHz)
/ low-speed (internal frequency: 5 kHz), low-speed (crystal frequency: 32.768 kHz) contained on the chip, the system clock can
be switched to high-speed frequency input (NORMAL mode) or to low-speed frequency input (SLOW mode).
The system clock is generated by dividing the oscillation clock. The best operation clock for the system can be selected by
switching its frequency ratio by programming. High speed mode has the standard mode which is based on the clock dividing
fxtl/frc by 2 (fxtl/2 or frc/2), and the double speed mode which is based on the clock not dividing fxtl or frc.
A machine cycle (minimum instruction execution time) in the standard mode is 200 ns when the original oscillation fxtl is
10 MHz. A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100
ns when fxtl is 10 MHz.
Product Summary
This datasheet describes the following model.
Model
MN101EF77G
ROM Size
128 KB
RAM Size
2 KB
Classification
Flash EEPROM version
Package
HQFP048-P-0707B
Publication date: June 2011
Ver. EM
1
MN101E77 Series
Features
ROM Size:
128 KB (131072
×
8-bit)
RAM Size:
2 KB (2048
×
8-bit)
Package:
48-HQFP (7 mm
×
7 mm, 0.50 mm pitch) *
*: halogen free package
Machine Cycle:
High speed mode 1 (External high speed oscillation) <fs = fxtl / 1>
0.125
ms
/ 8 MHz (2.0 V to 3.6 V)
0.250
ms
/ 4 MHz (V
RSTL
to 3.6 V)
High speed mode 2 (Internal high speed oscillation) <fs = frc / 2>
0.125
ms
/ 8 MHz (V
RSTL
to 3.6 V)
* It is necessary to set Handshake mode
Low speed mode 1 (External low speed oscillation) <fs = fxtls / 2>
61.04
ms
/ 32.768 kHz (V
RSTL
to 3.6 V)
Low speed mode 2 (Internal low speed oscillation) <fs = frcs / 2>
400
ms
/ 5 kHz (V
RSTL
to 3.6 V)
Clock Gear Circuit Embedded:
The operation speed of system clock can be changed by switching the dividing ratio of the oscillation clock (fosc,fx)
(1, 2, 4, 8, 16, 32, 64, 128 dividing)
* fosc : High speed clock switched between Internal and External High speed oscillation
fx : Low speed clock switched between Internal and External low speed oscillation
Oscillation Circuit:
External high speed oscillation (fxtl) : (crystal/ ceramic)
Internal high speed oscillation (frc) : 16 MHz
±
2 %
External low speed oscillation (fxtls) : (crystal)
Internal low speed oscillation (frcs) : 5 kHz
±
10 %
Operation Modes:
NORMAL mode (High-speed mode)
SLOW mode
(Low-speed mode)
HALT mode
(High-speed / Low-speed mode)
STOP mode
The operation clock can be switched in each mode.
ROM Correction:
Maximum of 3 parts in a program
Operation Voltage:
V
RSTL
to 3.6 V (V
RSTL
: Auto Reset Voltage 1.95 V
±
0.15 V)
Operating Temperature:
-20°C
to +60°C
2
Ver. EM
MN101E77 Series
Features (continued)
Interrupt:
24 interrupts
<External Interrupt> Rising / falling edge can be specified.
IRQ0 – External Interrupt (Edge selectable, Noise
filter
connectable)
IRQ1 – External Interrupt (Edge selectable, Noise
filter
connectable)
IRQ2 – External Interrupt (Edge selectable, Both edges selectable)
IRQ3 – External Interrupt (Edge selectable, Both edges selectable)
IRQ4 – External Interrupt (Edge selectable, Both edges selectable)
IRQ6 – External Interrupt (Key scan interrupt)
<Timer Interrupt>
TM0IRQ – Timer 0 interrupt (8-bit timer)
TM1IRQ – Timer 1 interrupt (8-bit timer)
TM2IRQ – Timer 2 interrupt (8 bit timer)
TM3IRQ – Timer 3 interrupt (8-bi timer)
TM6IRQ – Timer 6 interrupt (8-bi timer)
TM7IRQ – Timer 7 interrupt (16-bit timer)
T7OC2IRQ – Timer 7 compare register 2 interrupt (16-bit timer)
TM8IRQ – Timer 8 interrupt (16-bit timer)
T8OC2IRQ – Timer 8 compare register 2 interrupt (16-bit timer)
TBIRQ
－
Time base timer interrupt
<Serial Interface Interrupt>
SC0RIRQ – Serial 0 UART reception interrupt
(UART reception)
SC0TIRQ – Serial 0 UART transmission interrupt (UART transmission, synchronous)
SC1RIRQ – Serial 1 UART reception interrupt
(UART reception)
SC1TIRQ – Serial 1 UART transmission interrupt (UART transmission, synchronous)
SC4IRQ – Serial 4 interrupt (Multi master IIC communication, synchronous)
SC4STPCIRQ – Serial 4 interrupt (Multi master IIC stop condition)
<Overrun Interrupt>
NMI – Non-maskable interrupt
<A/D Conversion Interrupt>
ADIRQ – A/D conversion end
A/D Converter:
10-bit
×
9 channels
Gain-Amp:
2 channels
Reference Power Supply:
1.7 V
±
0.1 V
Voice-Amp:
ABclass Amp
Built in speaker disconnection detector circuit
Amplitude gain selectable
* Low pass
filter
for extracting voice signal from PWM output is not built in
Ver. EM
3
MN101E77 Series
Features (continued)
Timer Counter:
10 Timers (All timer counters generate interrupts.)
Timer 0 – 8-bit timer
Square wave output, PWM output, Simple pulse width measurement
Added pulse (2-bit) system PWM
Clock source : fosc, fosc/4, fosc/16, fosc/32, fosc/64, fs/2, fs/4, fx, external clock
Square wave output and PWM output can be output to the large current pin P30(TM0O)
Timer 1 – 8-bit timer
Timer 0 and 1 can be connected in cascade
Clock source : fosc, fosc/4, fosc/16, fosc/64, fosc/128, fs/2, fs/8, fx
Usable as UART baud rate timer
Timer 2 – 8-bit timer
Square wave output, PWM output, Simple pulse width measurement,
Added pulse (2-bit) system PWM,
Clock source : fosc, fosc/4, fosc/16, fosc/32, fosc/64, fs/2, fs/4, fx , external clock
Square wave output and PWM output can be output to the large current pin P32(TM2O).
Usable as UART baud rate timer
Timer 3 – 8-bit timer
Timer 2 and Timer 3 can be connected in cascade
Clock source : fosc, fosc/4, fosc/16, fosc/64, fosc/128, fs/2, fs/8, fx
Timer 6 – 8-bit timer
Timer 6 can be combined to Time base timer
Clock source : fosc, fs, fx, time base output (1/2
7
or 1/2
13
)
Timer 7 – 16-bit timer (Double buffer composition)
Square wave output, PWM output (duty/cycle continuous changeable),Event count,
Pulse width measurement, Input capture
PWM output can be output to the large current pin P31 (TM7O).
Clock source : Dividing fosc, fs, external clock in 1, 2, 4 or 16
Timer 8 – 16-bit timer (Double buffer composition)
Square wave output, PWM output (duty/cycle continuous changeable),Event count,
Pulse width measurement, Input capture
PWM output can be output to the large current pin P33 (TM8O).
Clock source: Dividing fosc, fs, external clock in 1, 2, 4 or 16
Time base timer
Clock source : fosc, fx
Interrupt generation cycle : fosc/2
7
, fosc/2
8
, fosc/2
9
, fosc/2
10
, fosc/2
12
, fosc/2
13
, fosc/2
14
, fosc/2
15
,
fx/2
7
, fx/2
8
, fx/2
9
, fx/2
10
, fx/2
12
, fx/2
13
, fx/2
14
, fx/2
15
Watchdog timer
Error detection cycle: selectable from fs/2
16
, fs/2
18
, and fs/2
20
.
Watchdog timer 2
Error detection cycle: selectable from frcs/2
11
, frcs/2
12
, frcs/2
14
, and frcs/2
16
.
Clock output:
OSC source oscillation, system clock or internal low-speed clock can be output.
4
Ver. EM
MN101E77 Series
Features (continued)
Serial Interface: 3 channel
<Serial interface 0>
CH0 – 3 channel type synchronous / UART (full duplex)
Transfer clock: 1/2 of fosc/2, fosc/4, fosc/16, fosc/64, fs/2, fs/4, timer1 or 2 output
At UART, timer1 or 2 are used as a baud rate timer
MSB/LSB can be selected as the
first
bit to be transferred.
Any transfer size from 1 to 8 bits can be selected.
Parity check, parity addition, overrun and framing error detection.
Usable as 2 channel type serial interface.
<Serial interface 1>
CH1 – 3 channel type synchronous / UART (full duplex)
Transfer clock: 1/2 of fosc/2, fosc/4, fosc/16, fosc/64, fs/2, fs/4, timer0 or 1 output
At UART, timer0 or 1 are used as a baud rate timer
MSB/LSB can be selected as the
first
bit to be transferred.
Any transfer size from 1 to 8 bits can be selected.
Parity check, parity addition, overrun and framing error detection.
Usable as 2 channel type serial interface.
<Serial interface 4>
CH4 – 3 channel type synchronous / Multi master IIC interface
Transfer clock: 1/2 of fosc/2, fosc/4, fosc/16, fosc/64, fs/2, fs/4, timer2 or 3 output
MSB/LSB can be selected as the
first
bit to be transferred.
Any transfer size from 1 to 8 bits can be selected.
Usable as 2 channel type serial interface.
7-bit or 10-bit slave address is available. (Multi master IIC)
Support general call communication mode. (Multi master IIC)
Buzzer output:
Output frequency can be selected from
fosc/2
14
, fosc/2
13
, fosc/2
12
, fosc/2
11
, fosc/2
10
, fosc/2
9
, fx/2
4
, fx/2
3
LED driver:
7 pins (3 pins are used for Nch open-drain output)
Ver. EM
5
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