Si5364
SONET/SDH P
R E C I S I O N
P
O R T
C
A R D
C
L O C K
IC
Features
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps
RMS
No external components (other than a
resistor and standard bypassing)
Up to three clock inputs
Four independent clock outputs at 19,
155, or 622 MHz
Stratum 3, 3E, and SMC compatible
Digital hold for loss-of-input clock
Automatic or manually-controlled hitless
switching between clock inputs
Revertive/non-revertive switching
Loss-of-signal and frequency offset
alarms for each clock input
Support for forward and reverse FEC
clock scaling
8 kHz frame sync output
Low power
Small size (11x11 mm)
Si5364
Bottom View
Applications
SONET/SDH line/port cards
Terabit routers
Core switches
Digital cross connects
Ordering Information:
See page 36.
Description
The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and
distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/
port cards. This device phase locks to one of three reference inputs in the range of
19.44 MHz and generates four synchronous clock outputs that can be independently
configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock).
Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality
with unparalleled performance while eliminating external loop filter components,
providing programmable loop parameters, and simplifying design. The on-chip reference
monitoring and clock switching functions support Stratum 3/3E and SMC compatible
clock switching with excellent output phase transient characteristics. FEC rates are
supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios.
The Si5364 establishes a new standard in performance and integration for ultra-low jitter
clock generation. It operates from a single 3.3 V supply.
Functional Block Diagram
REXT
VSEL33
VDD
GND
FEC[1:0]
BWSEL[1:0]
Biasing & Supply
CLKIN_A+
CLKIN_A–
CLKIN_B+
CLKIN_B–
REF/CLKIN_F+
REF/CLKIN_F–
LOS_A
FOS_A
LOS_B
FOS_B
LOS_F
DSBLFOS
SMC/S3N
VALTIME
AUTOSEL
RVRT
MANCNTRL[1:0]
INCDELAY
DECDELAY
FXDDELAY
A_ACTV
B_ACTV
DH_ACTV
F_ACTV
2
2
2
CAL_ACTV
÷
CLKOUT_1+
CLKOUT_1–
2
FRQSEL_1[1:0]
CLKOUT_2+
CLKOUT_2–
FRQSEL_2[1:0]
CLKOUT_3+
CLKOUT_3–
2
FRQSEL_3[1:0]
CLKOUT_4+
CLKOUT_4–
2
FRQSEL_4[1:0]
FSYNC
DSBLFSYNC
SYNCIN
2
SiLECT
TM
Switching
DSPLL
TM
÷
2
2
÷
Signal
Detection,
Selection,
& Control
÷
÷
RSTN/CAL
Rev. 2.2 7/04
Copyright © 2004 by Silicon Laboratories
Si5364
Si5364
T
A B L E O F
C
O N T E N TS
S
ECTION
P
AGE
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1. Clock Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3. Frequency Offset and Loss-of-Signal Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4. Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.5. Input Clock Select Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6. 8 kHz Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3. Pin Descriptions: Si5364 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6. 11x11 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 2.2
3
Si5364
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
Parameter
Ambient Temperature
Si5364 Supply Voltage
3
When Using 3.3 V Supply
Symbol
T
A
V
DD33
Test Condition
Min
1
–20
2
3.135
Typ
25
3.3
Max
1
85
3.465
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5364 is guaranteed by design to operate at –40
° C.
All electrical specifications are guaranteed for an ambient
temperature of –20° C to 85° C.
3.
The Si5364 specifications are guaranteed when using the recommended application circuit (including component
tolerance of Figure 7 on page 15.
4
Rev. 2.2
Si5364
CLKIN+
CLKIN–
V
IS
A. Operation with Single-Ended Clock Inputs*
*Note: W hen using single-ended clock sources, the unused clock
inputs on the Si5364 must be ac-coupled to ground.
CLKIN+
CLKIN–
0.5 V
ID
(CLKIN+) – (CLKIN–)
V
ID
B. Operation with Differential Clock Inputs
*Note: Transmission line termination, when required, must be
provided externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
t
F
t
R
Figure 2. Rise/Fall Time Measurement
Rev. 2.2
5
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