MMSF5P02HD
Preferred Device
Power MOSFET
5 Amps, 20 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the drain−to−source
diode has a very low reverse recovery time. MiniMOSt devices are
designed for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc−dc converters,
and power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery
Life
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Avalanche Energy Specified
•
Mounting Information for SO−8 Package Provided
8
1
L
Y
WW
= Location Code
= Year
= Work Week
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5 AMPERES
20 VOLTS
R
DS(on)
= 30 mW
P−Channel
D
G
S
MARKING
DIAGRAM
SO−8
CASE 751
STYLE 13
S5P02H
LYWW
PIN ASSIGNMENT
N−C
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
ORDERING INFORMATION
Device
MMSF5P02HDR2
Package
SO−8
Shipping
2500 Tape & Reel
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 4
1
Publication Order Number:
MMSF5P02HD/D
MMSF5P02HD
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage
−
Continuous
1″ SQ.
FR−4 or G−10 PCB
Thermal Resistance
−
Junction to Ambient
Total Power Dissipation @ T
A
= 25°C
Linear Derating Factor
Drain Current
−
Continuous @ T
A
= 25°C
Continuous @ T
A
= 70°C
Pulsed Drain Current (Note 2)
Thermal Resistance
−
Junction to Ambient
Total Power Dissipation @ T
A
= 25°C
Linear Derating Factor
Drain Current
−
Continuous @ T
A
= 25°C
Continuous @ T
A
= 70°C
Pulsed Drain Current (Note 2)
Symbol
V
DSS
V
DGR
V
GS
R
THJA
P
D
I
D
I
D
Max
20
20
±
8.0
50
2.5
20
8.7
7.0
43.5
80
1.56
12.5
6.9
5.5
35
−
55 to
150
1000
Unit
V
V
V
°C/W
Watts
mW/°C
A
A
A
°C/W
Watts
mW/°C
A
A
A
°C
mJ
10 seconds
Minimum
FR−4 or G−10 PCB
I
DM
R
THJA
P
D
I
D
I
D
10 seconds
I
DM
T
J
, T
stg
E
AS
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy
−
Starting T
J
= 25°C
(V
DD
= 20 Vdc, V
GS
= 4.5 Vdc, Peak I
L
= 19 Apk, L = 5.5 mH, R
G
= 25
W)
1. Negative sign for P−Channel devices omitted for clarity.
2. Repetitive rating; pulse width limited by maximum junction temperature.
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2
MMSF5P02HD
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk
≥
2.0)
(Notes 3 & 5)
V
(BR)DSS
Vdc
20
−
−
−
−
−
10
−
−
−
−
−
1.0
25
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Current
(V
DS
= 16 Vdc, V
GS
= 0 Vdc)
(V
DS
= 16 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
8.0 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(Cpk
≥
2.0)
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 4.5 Vdc, I
D
= 6.4 Adc)
(V
GS
= 2.5 Vdc, I
D
= 5.1 Adc)
On−State Drain Current
(V
DS
≤
5.0 V, V
GS
= 4.5 V)
(V
DS
≤
5.0 V, V
GS
= 2.5 V)
Forward Transconductance (V
DS
= 9.0 Vdc, I
D
= 6.4 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
See Figure 8
(V
DD
= 6.0 Vdc, I
D
= 1.0 Adc,
V
GS
= 4.5 Vdc,
R
G
= 6.0
Ω)
(Note 3)
(V
DS
= 16 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
(Note 3)
(Cpk
≥
2.0)
(Notes 3 & 5)
I
DSS
I
GSS
V
GS(th)
nAdc
Vdc
0.7
−
−
−
10
5.0
14
−
−
−
−
−
−
−
−
−
−
−
0.9
2.6
22
35
−
−
18
1400
925
370
19
28
130
90
27.3
3.4
12
8.0
1.4
−
30
45
mV/°C
mΩ
(Notes 3 & 5)
R
DS(on)
I
D(on)
A
−
−
−
1960
1300
520
40
55
200
150
38
−
−
−
Vdc
−
−
−
−
−
−
0.77
0.6
95
35
60
0.151
1.2
−
180
−
−
−
μC
ns
nC
ns
Mhos
pF
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
(V
DS
= 6.0 Vdc, I
D
= 6.4 Adc,
V
GS
= 4.5 Vdc) (Note 3)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(I
S
= 2.5 Adc, V
GS
= 0 Vdc) (Note 3)
(I
S
= 2.5 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
V
SD
Reverse Recovery Time
See Figure 15
t
rr
(I
S
= 2.5 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs) (Note 3)
t
a
t
b
Q
RR
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
Max limit
−
Typ
5. Reflects typical values.
C
pk
=
3 x SIGMA
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3
MMSF5P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
I D , DRAIN CURRENT (AMPS)
8.0
6.0
4.0
2.0
1.7 V
0
0
0.5
1.0
1.5
2.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
1.0
1.5
2.0
2.5
3.0
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
4.5 V
12
2.5 V
2.7 V
3.1 V
3.7 V
2.1 V
2.3 V
ID, DRAIN CURRENT (AMPS)
T
J
= 25°C
10
8.0
6.0
100°C
4.0
2.0
25°C
T
J
= −55°C
V
DS
≥
10 V
V
GS
=
8
1.9 V
Figure 1. On−Region Characteristics
R DS(on)
(W)
, DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.06
I
D
= 6.4 A
T
J
= 25°C
0.04
R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.06
Figure 2. Transfer Characteristics
T
J
= 25°C
0.04
2.5 V
V
GS
= 4.5 V
0.02
0.02
0
0
2.0
4.0
6.0
8.0
10
V
GS
, GATE−TO−SOURCE (VOLTS)
0
0
2.0
4.0
6.0
8.0
10
12
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
V
GS
= 4.5 V
I
D
= 5.1 A
1.5
V
GS
= 0 V
T
J
= 125°C
IDSS , LEAKAGE (nA)
100
100°C
25°C
1.0
10
0.5
0
−50
1.0
−25
0
25
50
75
100
125
150
0
4.0
8.0
12
16
20
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
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4
Figure 6. Drain−to−Source Leakage Current
versus Voltage
MMSF5P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
6000
C
iss
C, CAPACITANCE (pF)
C
rss
T
J
= 25°C
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
4000
2000
C
iss
C
oss
C
rss
0
−10
V
GS
0 V
DS
10
20
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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