74ALVCH32973
16-bit bus transceiver and transparant D-type latch with 8
independent buffers
Rev. 3 — 17 January 2013
Product data sheet
1. General description
The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8
independent buffers with bus hold inputs and 3-state outputs. It features direction (1DIR,
2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch
enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two
8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buffer with data inputs Dn and
outputs Yn. The configuration of the control pins allows the device to be used as one 8-bit
buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit
transceiver and one 16-bit latch.
The 8-bit buffer functions independently of the control inputs. The direction of data
transmission between A and B is controlled by nDIR and when nTOE is set HIGH the A
and B ports will assume a HIGH-impedance OFF-state, they will be effectively isolated.
When nLE is HIGH, data at the A inputs enter the latches. In this condition the latches are
transparent, a Q output will change each time its corresponding A-input changes. When
nLE is LOW the latches store the information that was present at the inputs a set-up time
preceding the HIGH-to-LOW transition of nLE. A HIGH on nLOE causes the Q outputs to
assume a high-impedance OFF-state. Operation of the nLOE input does not affect the
state of the latches.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50
transmission lines at 85
C
Current drive
24
mA at V
CC
= 3.0 V
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
3. Ordering information
Table 1.
Ordering information
Temperature range
40 C
to +85
C
Package
Name
74ALVCH32973EC
LFBGA96
Description
plastic low profile fine-pitch ball grid array
package; 96 balls; body 13.5
5.5
1.05 mm
Version
SOT536-1
Type number
4. Functional diagram
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Fig 1.
Logic symbol
V
CC
data input
to internal circuit
mna705
Fig 2.
Bus hold circuit
74ALVCH32973
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 17 January 2013
2 of 17
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
5. Pinning information
5.1 Pinning
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Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
nTOE (n = 1 to 2)
nDIR (n = 1 to 2)
nLE (n = 1 to 2)
nLOE (n = 1 to 2)
1A[0:7]
D[0:7]
1B[0:7]
2B[0:7]
Y[0:7]
1Q[0:7]
2A[0:7]
2Q[0:7]
GND
V
CC
Pin description
Ball
A3, J3
A4, J4
H3, T3
H4, T4
A1, B1, C1, D1, E1, F1,G1, H1
A2, C2, E2, G2, J2, L2, N2, R2
A5, B5, C5, D5, E5, F5, G5, H5
J5, K5, L5, M5, N5, P5, R5, T5
B2, D2, F2, H2, K2, M2, P2, T2
A6, B6, C6, D6, E6, F6, G6, H6
J1, K1, L1, M1, N1, P1, R1, T1
J6, K6, L6, M6, N6, P6, R6, T6
Description
transceiver output enable input (active LOW)
direction control input (active HIGH)
latch enable input (active HIGH)
latch output enable input (active LOW)
data input/output
data input
data input/output
data input/output
data output
data output
data input/output
data output
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V)
M3, M4, N3, N4, R3, R4
C3, C4, F3, F4, L3, L4, P3, P4
supply voltage
74ALVCH32973
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 17 January 2013
3 of 17
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
6. Functional description
6.1 Function table
Table 3.
Inputs
nLOE
L
L
L
L
L
H
H
H
H
H
[1]
Function table
[1]
Internal latches Outputs nQn
nLE
H
H
L
H
H
L
nAn
L
H
l
h
X
l
h
L
H
X
L
H
L
H
no change
L
H
L
H
no change
L
H
L
H
no change
Z
Z
Z
Z
Z
enable register and disable
outputs
hold mode and disable outputs
hold mode
latch register and disable outputs
enable and read register
(transparent mode)
latch and read register
Operating mode
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
= negative-going transition;
Z = high-impedance OFF-state;
X = don’t care.
Table 4.
Inputs
nTOE
L
L
H
[1]
Function table
[1]
Outputs
nDIR
L
H
X
nAn
nAn = nBn
input
Z
nBn
input
nBn = nAn
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Table 5.
Input
Dn
L
H
[1]
Function table
[1]
Output
Yn
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74ALVCH32973
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 17 January 2013
4 of 17
NXP Semiconductors
74ALVCH32973
16-bit bus transceiver and transparant D-type latch; 8 buffers
7. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
control inputs
data inputs
V
O
> V
CC
or V
O
< 0 V
[1]
[1]
[1]
Min
0.5
50
0.5
0.5
-
0.5
-
-
100
65
Max
+4.6
-
+4.6
V
CC
+ 0.5
50
V
CC
+ 0.5
50
100
-
+150
1000
Unit
V
mA
V
V
mA
V
mA
mA
mA
C
mW
V
O
= 0 V to V
CC
T
amb
=
40 C
to +85
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 70
C
the value of P
tot
derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 7.
Symbol
V
CC
Recommended operating conditions
Parameter
supply voltage
Conditions
maximum speed performance
C
L
= 30 pF
C
L
= 50 pF
low voltage applications
V
I
V
O
T
amb
t/V
input voltage
output voltage
ambient temperature
in free air
V
CC
= 3.0 V to 3.6 V
input transition rise and fall rate V
CC
= 2.3 V to 3.0 V
2.3
3.0
1.2
0
0
40
0
0
-
-
-
-
-
-
-
-
2.7
3.6
3.6
V
CC
V
CC
+85
20
10
V
V
V
V
V
C
ns/V
ns/V
Min
Typ
Max
Unit
74ALVCH32973
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 17 January 2013
5 of 17
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