MMSF1310
Preferred Device
Power MOSFET
10 Amps, 30 Volts
N−Channel SO−8
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the drain−to−source
diode has a very low reverse recovery time. MiniMOSt devices are
designed for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc−dc converters,
and power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
•
Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
•
High Speed Switching Provides High Efficiency for DC/DC
Converter
•
Miniature SO−8 Surface Mount Package − Saves Board Space
•
Diode Exhibits High Speed, With Soft Recovery
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage − Continuous
Continuous Drain Current @ T
A
= 25°C
(Note 1.)
Pulsed Drain Current (Note 2.)
Total Power Dissipation @ T
A
= 25°C
(Note 1.)
Operating and Storage Temperature Range
Symbol
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
J
, T
stg
Max
30
30
±
20
10
50
2.5
− 55 to
150
W
°C
L
Y
WW
= Location Code
= Year
= Work Week
Unit
Vdc
Vdc
Vdc
Adc
1
8
SO−8
CASE 751
STYLE 12
S1310
LYWW
http://onsemi.com
10 AMPERES
30 VOLTS
R
DS(on)
= 15 mW
N−Channel
D
G
S
MARKING
DIAGRAM
PIN ASSIGNMENT
THERMAL RESISTANCE
Junction−to−Ambient (Note 1.)
R
θJA
50
°C/W
1. When mounted on 1″ square FR−4 or G−10 board
(V
GS
= 10 V, @ 10 Seconds)
2. Repetitive rating; pulse width limited by maximum junction temperature.
Source
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
ORDERING INFORMATION
Device
MMSF1310R2
Package
SO−8
Shipping
2500 Tape & Reel
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2000
1
September, 2004 − Rev. XXX
Publication Order Number:
MMSF1310/D
MMSF1310
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 10 Adc)
(V
GS
= 4.5 Vdc, I
D
= 5.0 Adc)
Forward Transconductance (V
DS
= 5.0 Vdc, I
D
= 1.0 Adc) (Note 3.)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 15 Vdc, I
D
= 10 Adc,
V
GS
= 10 Vdc) (Note 3.)
(V
DD
= 24 Vdc, I
D
= 10 Adc,
V
GS
= 10 Vdc,
Vdc
R
G
= 6.0
Ω)
(Note 3.)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 10 Adc, V
GS
= 0 Vdc) (Note 3.)
(I
S
= 10 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 10 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/µs) (Note 3.)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperatures.
5. Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
6. Repetitive rating; pulse width limited by maximum junction temperature.
t
a
t
b
Q
RR
−
−
−
−
0.82
0.67
52
23
30
0.05
1.0
−
−
−
−
−
µC
ns
Vdc
−
−
−
−
−
−
−
−
10
36
82
95
48
3.0
4.0
7.0
20
72
164
190
68
−
−
−
nC
ns
(V
DS
= 24 Vdc, V
GS
= 0 V,
Vd
V
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
1440
680
195
2020
960
280
pF
V
GS(th)
1.0
−
R
DS(on)
−
−
g
FS
−
9.5
12.5
5.0
15
19
−
Mhos
1.3
4.4
2.5
−
Vdc
mV/°C
mΩ
V
(BR)DSS
30
−
I
DSS
−
−
I
GSS
−
−
−
−
1.0
10
100
nAdc
−
27
−
−
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
http://onsemi.com
2
MMSF1310
TYPICAL ELECTRICAL CHARACTERISTICS
20
10 V
ID , DRAIN CURRENT (AMPS)
16
3.1 V
3.5 V
4.5 V
12
2.7 V
2.9 V
T
J
= 25°C
ID, DRAIN CURRENT (AMPS)
16
20
V
DS
≥
10 V
12
T
J
= 125°C
25°C
− 55°C
4
0
8
V
GS
= 2.3 V
8
4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R DSon(
W
) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.05
I
D
= 10 A
T
J
= 25°C
0.02
T
J
= 25°C
0.015
V
GS
= 4.5 V
10 V
0.04
0.03
0.01
0.02
0.01
0.005
0
0
2
4
6
8
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
0
1
2
3
I
D
, DRAIN CURRENT (AMPS)
4
5
Figure 3. On−Resistance versus
Drain Current
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
V
GS
= 10 V
I
D
= 10 A
1.5
IDSS , LEAKAGE (A)
1E−06
T
J
= 125°C
1E−07
100°C
1E−08
1.0
1E−09
25°C
0.5
1E−10
V
GS
= 0 V
0
−50
1E−11
−25
0
25
50
75
100
125
150
0
T
J
, JUNCTION TEMPERATURE (°C)
10
20
25
5
15
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
30
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
http://onsemi.com
3
MMSF1310
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
4000
V
DS
= 0 V
C
iss
C, CAPACITANCE (pF)
3000
C
rss
2000
V
GS
= 0 V
C
oss
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance
(Figure 8) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure
is taken with a resistive load, which approximates an
optimally snubbed inductive load. Power MOSFETs may be
safely operated into an inductive load; however, snubbing
reduces switching losses.
T
J
= 25°C
1000
C
rss
0
−10
−5
V
GS
0
V
DS
5
10
15
20
25
30
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
4
MMSF1310
1000
T
J
= 25°C
I
D
= 10 A
V
DD
= 24 V
V
GS
= 10 V
100
t, TIME (ns)
t
f
t
d(off)
t
r
10
t
d(on)
1
1
10
R
G
, GATE RESISTANCE (OHMS)
100
Figure 8. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 10. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
10
V
GS
= 0 V
T
J
= 25°C
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
IS , SOURCE CURRENT (AMPS)
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Diode Forward Voltage versus Current
http://onsemi.com
5
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
