P-Channel Enhancement Mode Field Effect Transistor
FEATURES
-30V, -13A, R
DS(ON)
= 10mΩ @V
GS
= -10V.
R
DS(ON)
= 15.5mΩ @V
GS
= -4.5V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead free product is acquired.
Surface mount Package.
D
8
CEM3083
PRELIMINARY
D
7
D
6
D
5
SO-8
1
1
S
2
S
3
S
4
G
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
T
A
= 25 C unless otherwise noted
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
,T
stg
Limit
-30
Units
V
V
A
A
W
C
±
20
-13
-52
2.5
-55 to 150
Maximum Power Dissipation
Operating and Store Temperature Range
Parameter
Thermal Resistance, Junction-to-Ambient
b
Symbol
R
θJA
Limit
50
Units
C/W
This is preliminary information on a new product in development now .
Details are subject to change without notice .
1
Rev 1. 2007.Jun.
http://www.cetsemi.com
CEM3083
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
b
Drain-Source Diode Forward Voltage
c
d
d
c
T
A
= 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
V
GS
= 0V, I
S
= -1.3A
V
DS
= -15V, I
D
= -13A,
V
GS
= -5V
Test Condition
V
GS
= 0V, I
D
= -250µA
V
DS
= -30V, V
GS
= 0V
V
GS
= 20V, V
DS
= 0V
V
GS
= -20V, V
DS
= 0V
V
GS
= V
DS
, I
D
= -250µA
V
GS
= -10V, I
D
= -13A
V
GS
= -4.5V, I
D
= -10A
V
DS
= -15V, I
D
= -13A
V
DS
= -15V, V
GS
= 0V,
f = 1MHz
-1
8
12.5
40
3450
465
365
18.8
11.2
132
63
37.9
9.6
13.3
-1.3
-1.1
37.6
22.4
264
126
50
Min
-30
-1
100
-100
-3
10
15.5
Typ
Max
Units
V
µA
5
nA
nA
V
mΩ
mΩ
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
Gate Threshold Voltage
Forward Transconductance
V
DD
= -15V, I
D
= -13A,
V
GS
= -10V, R
GEN
= 6Ω
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.
2
CEM3083
10
20
-V
GS
=10,8,6,4V
-I
D
, Drain Current (A)
-V
GS
=2.4V
6
4
2
0
-I
D
, Drain Current (A)
8
16
12
8
25 C
4
0
T
J
=125 C
-55 C
3
4
5
6
-V
GS
=2V
0
0.1
0.2
0.3
0.4
0.5
0.6
0
1
2
-V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
6000
5000
4000
3000
2000
1000
0
Crss
0
5
10
15
20
Coss
25
30
Ciss
2.2
1.9
1.6
1.3
1.0
0.7
0.4
-100
-V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
I
D
=-13A
V
GS
=-10V
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
-V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
V
DS
=V
GS
10
2
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
-I
S
, Source-drain current (A)
V
GS
=0V
V
TH
, Normalized
Gate-Source Threshold Voltage
I
D
=-250µA
10
1
10
0
-25
0
25
50
75
100
125
150
10
-1
0.4
0.6
0.8
1.0
1.2
1.4
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
-V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEM3083
-V
GS
, Gate to Source Voltage (V)
5
4
3
2
1
0
V
DS
=-15V
I
D
=-13A
10
2
R
DS(ON)
Limit
-I
D
, Drain Current (A)
10ms
100ms
1s
10
1
10
0
DC
5
10
-1
0
8
16
24
32
40
10
-2
T
A
=25 C
T
J
=150 C
Single Pulse
10
-2
10
-1
10
0
10
1
10
2
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DD
t
on
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
t
d(on)
V
OUT
-V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
t
off
t
r
90%
t
d(off)
90%
10%
t
f
10%
INVERTED
90%
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
10
0
r(t),Normalized Effective
Transient Thermal Impedance
D=0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
10
-1
10
-2
Single Pulse
10
-3
1. R
θJA
(t)=r (t) * R
θJA
2. R
θJA
=See Datasheet
3. T
JM-
T
A
= P* R
θJA
(t)
4. Duty Cycle, D=t1/t2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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