1:2, Differential-to-LVCMOS/LVTTL Zero
Delay Clock Generator
87002-02
DATA SHEET
General Description
The 87002-02 is a highly versatile 1:2 Differential-to-
LVCMOS/LVTTL Clock Generator. The 87002-02 has a differential
clock input. The CLK, nCLK pair can accept most standard
differential input levels. Internal bias on the nCLK input allows the
CLK input to accept LVCMOS/LVTTL. The 87002-02 has a fully
integrated PLL and can be configured as zero delay buffer, multiplier
or divider and has an input and output frequency range of
15.625MHz to 250MHz. The reference divider, feedback divider and
output divider are each programmable, thereby allowing for the
following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve “zero delay”
between the input clock and the output clocks. The PLL_SEL pin can
be used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL and into
the internal output dividers.
Features
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Two LVCMOS/LVTTL outputs, 7
typical output impedance
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
Internal bias on nCLK to support LVCMOS/LVTTL levels on CLK
input
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: -10ps ± 150ps (3.3V ± 5%)
Full 3.3V or 2.5V operating supply
5V tolerant inputs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Industrial temperature information available upon request
Block Diagram
PLL_SEL
Pullup
Pin Assignment
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
Q0
GND
Q0
V
DDO
SEL0
SEL1
SEL2
SEL3
V
DD
CLK
nCLK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
GND
V
DDO
nc
MR
FB_IN
PLL_SEL
V
DDA
GND
0
CLK
Pulldown
nCLK
Pullup/Pulldown
1
Q1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
Pulldown
87002-02
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm package body
G Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
87002-02 Rev C 7/13/15
1
©2015 Integrated Device Technology, Inc.
87002-02 DATA SHEET
Table 1. Pin Descriptions
Number
1, 11, 18
2, 19
3, 17, 20
4, 5,
6, 7
8
9
10
12
13
Name
GND
Q0, Q1
V
DDO
SEL0, SEL1,
SEL2, SEL3
V
DD
CLK
nCLK
V
DDA
PLL_SEL
Power
Output
Power
Input
Power
Input
Input
Power
Input
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Power supply ground.
Single-ended clock outputs. 7
typical output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Core supply pin.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock (PLL Bypass). When HIGH, selects
PLL (PLL enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the outputs to go low. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
No connect.
14
FB_IN
Input
Pulldown
15
16
MR
nc
Input
Unused
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation
Capacitance (per output)
Output Impedance
V
DD
, V
DDA
, V
DDO
= 3.465V
V
DD
, V
DDA
, V
DDO
= 2.625V
5
7
Test Conditions
Minimum
Typical
4
51
51
23
17
12
Maximum
Units
pF
k
k
pF
pF
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
2
Rev C 7/13/15
87002-02 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
100
16
6
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDA
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
96
15
6
Units
V
V
V
mA
mA
mA
1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK
GENERATOR
5
Rev C 7/13/15
stm32/stm8
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