TSC87251G1A
Extended 8–bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC87251G1A products are derivatives of the
T
EMIC
Microcontroller family based on the extended
8–bit C251 Architecture. This family of products is
tailored to 8–bit microcontroller applications requiring
an increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size
reduction when compiling C programs while fully
preserving the legacy of C51 assembly routines.
The TSC87251G1A derivatives are pin–out and
software compatible with standard 80C51/Fx/Rx with
extended on–chip data memory (1 Kbyte RAM),
on–chip memory (16 Kbytes EPROM/OTPROM) and
up to 256 Kbytes of external code and data.
They provide transparent enhancements to Intel’s
87C251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I
2
C,
µWire
and SPI
protocols), a Keyboard interrupt interface and Power
Monitoring and Management features.
Notes:
This Datasheet provides the technical description of the TSC87251G1A derivatives. For further information on the device usage, please request
the TSC80251 Programmers’ Guide and the TSC80251G1 Design Guide.
For information on the Mask ROM and ROMless devices, please refer to the TSC87251G1D Datasheet.
2. Typical Applications
D
ISDN terminals
D
High–Speed modems
D
PABX (SOHO)
D
Networking
D
Line cards
D
Computer peripherals
D
Printers
D
Plotters
D
Scanners
D
Banking machines
D
Barcode readers
D
Smart cards readers
D
High–end digital monitors
D
High–end joysticks
Purchase of TEMIC I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
Rev. A
–
September 21, 1998
1
TSC87251G1A
3. Features
D
Pin–Out and software compatibility with standard
80C51 products and 80C51FA/FB/RA/RB
D
Plug–in replacement of Intel’s 80C251Sx
D
C251 core:
G
G
G
G
G
Intel’s MCS
R
251
step A compliance
125 ns Instruction cycle time at 16 MHz
40–byte Register File
Registers Accessible as Bytes, Words or Dwords
Six–stage instruction Pipeline
16–bit Internal Code Fetch
D
Secured 14–bit Hardware Watchdog Timer
D
Power Monitoring and Management
G
Power–Fail reset
G
Power–On reset (integrated on the chip)
G
Power–Off flag (cold and warm resets)
G
Software programmable system clock
G
Idle and Power–Down modes
D
Keyboard interrupt interface on Port 1
D
ONCE mode and full speed Real–Time In–Circuit
Emulation support (Third Party Vendors)
D
Speed ranges:
G
0 to 16 MHz
D
Supply ranges:
G
5 V
±10
%
D
Temperature ranges:
G
Commercial (0°C to +70°C)
G
Industrial (–40°C to +85°C)
G
Option: extended range (–55°C to +125°C)
D
Packages:
G
PDIL 40, PLCC 44
G
UV–Window CQPJ 44
G
Options: known good dice and ceramic packages
D
Enriched C51 Instruction Set
G
16–bit and 32–bit ALU
G
Compare and Conditional Jump Instructions
G
Expanded Set of Move Instructions
D
Linear Addressing
D
1 Kbyte of on–chip RAM
D
External memory space (Code/Data) programmable
from 64 Kbytes to 256 Kbytes
D
TSC87251G1A: 16 Kbytes of on–chip EPROM/
OTPROM (production with TSC83251G1D:
on–chip masked ROM version)
D
SINGLE–PULSE Programming Algorithm
D
Four 8–bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the
standard 80C51)
D
Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
D
SSLC: Synchronous Serial Link Controller
G
I
2
C master only protocol
G
µWire
and SPI master only protocol
D
Three 16–bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
D
EWC: Event and Waveform Controller
G
Compatible with Intel’s Programmable Counter
Array (PCA)
G
Common 16–bit Timer/Counter reference with
four possible clock sources (Fosc/4, Fosc/12,
Timer 1 and external input)
G
Five modules with four programmable modes:
– 16–bit software Timer/Counter
– 16–bit Timer/Counter Capture Input and
software pulse measurement
– High–speed output and 16–bit software Pulse
Width Modulation (PWM)
– 8–bit hardware PWM without overhead
G
16–bit Watchdog Timer/Counter capability
2
Rev. A
–
September 21, 1998
TSC87251G1A
4. Block Diagram
P3(A16) P2(A15–8) P1(A17)
P0(AD7–0)
PSEN#
PORTS 0–3
ALE/PROG#
UART
16–bit Memory Code
16–bit Memory Address
EA#/VPP
Event and Waveform
Controller
EPROM
OTPROM
16 Kbytes
RAM
1 Kbyte
Timers 0, 1 and 2
Bus Interface Unit
Peripheral Interface Unit
I
2
C/SPI/mWire
Controller
Watchdog Timer
24-bit Prog. Counter Bus
24-bit Data Address Bus
16-bit Inst. Bus
RST
8-bit Internal Bus
Power Monitoring
XTAL2
Clock Unit
Clock System Prescaler
XTAL1
8-bit Data Bus
Keyboard Interface
CPU
Interrupt Handler
Unit
VDD
VSS
VSS1
VSS2
Figure 1. TSC87251G1A Block Diagram
Rev. A
–
September 21, 1998
3
TSC87251G1A
5. Pin Description
5.1. Pinout
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
TSC87251G1A
Figure 2. TSC87251G1A 40–pin DIP package
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TSC87251G1A
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NC
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
Figure 3. TSC87251G1A 44–pin PLCC/CQPJ Package
4
Rev. A
–
September 21, 1998
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
18
19
20
21
22
23
24
25
26
27
28
TSC87251G1A
Table 1. TSC87251G1A
Pin Assignment
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS1
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2/MISO
Name
DIP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PLCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSS2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN#
ALE/PROG#
NC
EA#/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
Name
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
P3.0/RXD
NC
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
5.2. Signals
Table 2. TSC87251G1A
Signal Descriptions
Signal
Name
A17
Type
O
18
th
Address Bit
Description
Alternate
Function
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
A16
O
17
th
Address Bit
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
A15:8
(1)
AD7:0
(1)
ALE
O
I/O
O
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information are
available onlines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address
from address/databus.
CEX4:0
O
PCA Input/Output pins
CEXx are input signals for the PCA capture mode and output signals for the PCA compare and
PWM modes.
EA#
I
External Access Enable
EA# directs program memory accesses to on–chip or off–chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip EPROM/OTPROM if the address is within the range of the on–
chip EPROM/OTPROM; otherwise the access is off-chip. The value of EA# is latched at reset.
P1.7:3
P0.7:0
P2.7:0
P3.7
Rev. A
–
September 21, 1998
5
FPGA/CPLD
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