SPICE Device Model SUM110N04-2m7H
Vishay Siliconix
N-Channel 40-V (D-S) 175°C MOSFET
CHARACTERISTICS
•
N-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
gd
model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72933
09-Jun-04
www.vishay.com
1
SPICE Device Model SUM110N04-2m7H
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
V
GS(th)
I
D(on)
a
Symbol
Test Conditions
Simulated
Data
3.7
1170
0.0022
0.0031
0.0036
87
1
Measured
Data
Unit
V
DS
= V
GS
, I
D
= 250
µA
V
DS
= 5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 30 A
V
A
0.0022
Ω
Drain-Source On-State Resistance
r
DS(on)
V
GS
= 10 V, I
D
= 30 A, T
J
= 125°C
V
GS
= 10 V, I
D
= 30 A, T
J
= 175°C
Forward Transconductance
a
Forward Voltage
a
b
g
fs
V
SD
V
DS
= 15 V, I
D
= 30 A
I
S
= 85 A, V
GS
= 0 V
S
1.1
V
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
c
Gate-Source Charge
Gate-Drain Charge
c
Turn-On Delay Time
Rise Time
c
c
c
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 30 V, R
L
= 0.27
Ω
I
D
≅
110 A, V
GEN
= 10 V, R
G
= 2.5
Ω
V
DS
= 30 V, V
GS
= 10 V, I
D
= 110 A
V
GS
= 0 V, V
DS
= 25 V, f = 1 MHz
12450
1429
786
262
95
57
43
101
75
43
15720
1400
800
250
95
57
50
150
70
25
Ns
NC
Pf
Turn-Off Delay Time
c
Fall Time
c
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
2
Document Number: 72933
09-Jun-04
SPICE Device Model SUM110N04-2m7H
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 72933
09-Jun-04
www.vishay.com
3
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
